| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IMQ, IE, MVE, CQ (Joint) [detail] |
2019-03-14 15:10 |
Kagoshima | Kagoshima University | Study of Ultra-low-latency Video Coding Method for Autonomous Vehicles Kaito Mori, Seiji Mochizuki (Nihon Univ.), Kousuke Imamura, Koji Yogiashi, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.)  IMQ2018-41 IE2018-125 MVE2018-72 |
Applications such as autonomous driving and virtual reality (VR) require low-latency transfer of high definition (HD) vi... [more] | IMQ2018-41 IE2018-125 MVE2018-72 pp.109-114 |
| CS, IE, IPSJ-AVM, ITE-BCT [detail] | 2018-11-29 13:25 |
Tokushima | Tokushima University (Memorial Hall of Almuni(Engineering)) | Image Denoising by Non-local Means Using Half-pixel Yusuke Kaniyashiki, Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.) CS2018-75 IE2018-54 |
We propose a new noise reduction method based on non-local means using the pixels at half-pixel position. The performan... [more] |
CS2018-75 IE2018-54 pp.33-38 |
| CS | 2018-07-13 10:30 |
Okinawa | Eef Information Plaza (Kumejima Is.) | A Study of Video-coding for Ultra-low Latency Network Transmission Kaito Mori, Seiji Mochizuki (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) CS2018-37 |
Autonomous driving for vehicles and MR(Mixed Reality) for IoT(Internet of Things) equipment require ultra-low-latency vi... [more] | CS2018-37 pp.121-126 |
| VLD, HWS (Joint) |
2018-02-28 15:25 |
Okinawa | Okinawa Seinen Kaikan | Architecture of Full-HD 60-fps Real-time Optical Flow Processor Satoshi Kanda (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-99 |
This paper describes the architecture design of Full-HD 60fps real-time optical flow processor. In this processor, the W... [more] | VLD2017-99 pp.61-66 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-19 10:40 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) VLD2017-79 CPSY2017-123 RECONF2017-67 |
This paper describes the design and implementation of a real-time optical flow processor using a single field-programmab... [more] | VLD2017-79 CPSY2017-123 RECONF2017-67 pp.101-106 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-08 09:00 |
Kumamoto | Kumamoto-Kenminkouryukan Parea | A Packet Lookup Engine LSI with Automatic Rule Registration and Deletion Function Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2017-55 DC2017-61 |
[more] | VLD2017-55 DC2017-61 pp.171-176 |
| IE, ITE-ME, ITE-AIT [detail] | 2017-10-05 17:30 |
Nagasaki | Weight Function of Non-local Means Considering Image Characteristic for Poisson Noise Reduction Kousuke Imamura, Naoki Kimura, Yoshio Matsuda (Kanazawa Univ.) IE2017-57 |
In this paper, we propose a new weight function of non-local means for Poisson noise reduction from an image. The conven... [more] | IE2017-57 pp.59-64 |
|
| EE | 2016-11-28 13:30 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Poster Presentation]
Study of Ultra-low voltage oscillator for Energy Harvesting Satoshi Hashimoto, Tsutomu Yoshimura, Takao Kihara, Hiroshi Makino, Shuhei Iwade (Osaka Tech), Yoshio Matsuda (Kanazawa Univ.) EE2016-35 |
Recently, the energy harvesting such as the power generation with the electromagnetic wave energy and the thermoelectric... [more] | EE2016-35 pp.29-33 |
| VLD, CAS, MSS, SIP | 2016-06-17 10:30 |
Aomori | Hirosaki Shiritsu Kanko-kan | An FPGA Implementation of Real-time Optical Flow Estimation Processor Yu Suzuki, Masato Ito, Satoshi Kanda, Tetsuya Matsumura (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.) CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21 |
A real-time optical flow processor has been implemented using single FPGA chip. By introducing four effective methods, m... [more] | CAS2016-21 VLD2016-27 SIP2016-55 MSS2016-21 pp.115-120 |
| VLD | 2016-03-01 09:00 |
Okinawa | Okinawa Seinen Kaikan | A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) VLD2015-118 |
Developing an extremely efficient packet inspection algorithm for lookup engines is important to realize a high throughp... [more] | VLD2015-118 pp.43-48 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 16:15 |
Miyagi | A Design of the 178-MHz WXGA 30-fps Optical Flow Processor Based on HOE Algorithm Tetsuya Matsumura (Nihon Univ.), Aoi Kurokawa, Kosuke Imamura, Yoshio Matsuda (Kanazawa Univ.) VLD2015-32 ICD2015-45 IE2015-67 |
We propose an optical flow processor, which allows real-time processing of WXGA 30-fps at 178.3 MHz. By introducing the ... [more] | VLD2015-32 ICD2015-45 IE2015-67 pp.31-36 |
|
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | The LSI Implementation of a Memory Based Field Programmable Device for MCU Peripherals Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Hiroshi Makino (OIT), Kazutami Arimoto (Okayama Prefectural Univ.) VLD2014-108 DC2014-62 |
A Field Programmable Sequencer and Memory (FPSM), which is an embedded memory based programmable device for peripherals ... [more] | VLD2014-108 DC2014-62 pp.239-244 |
| IE, ITE-AIT, ITE-ME [detail] | 2014-11-07 10:00 |
Kagoshima | A study on improvement of microcalcification attenuation in medical image denoising using NL-means Tsuyoshi Yamashita (Kanazawa Univ.), Mamoru Ogaki (EIZO Co.), Marina Katou, Kousuke Imamura, Yoshio Matsuda, Shigeru Sanada (Kanazawa Univ.) IE2014-57 |
Image processing technology in medical field is attracting attention as a solution to realize improvement of diagnosis a... [more] | IE2014-57 pp.45-50 |
|
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2013-10-07 10:30 |
Aomori | A Memory Based Filed Programmable Device for Energy saving MCUs Tetsuya Matsumura (Nihon Univ.), Yoshifumi Kawamura (Renesas Electronics), Naoya Okada (Kanazawa Univ.), Kazutami Arimoto (Okayama Prefectual Univ.), Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) VLD2013-46 ICD2013-70 IE2013-46 |
A Field Programmable Sequencer and memory (FPSM), which is an embedded memory based programmable peripherals for Micro C... [more] | VLD2013-46 ICD2013-70 IE2013-46 pp.1-6 |
|
| SDM, ICD | 2013-08-02 09:50 |
Ishikawa | Kanazawa University | A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii (Renesas Electronics), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) SDM2013-76 ICD2013-58 |
[more] | SDM2013-76 ICD2013-58 pp.53-57 |
| SDM, ICD | 2013-08-02 16:30 |
Ishikawa | Kanazawa University | Affine motion model estimation processor applied to face parts tracking Shunsuke Morita, Masayuki Miyama, Yoshio Matsuda (Kanazawa Univ.) SDM2013-86 ICD2013-68 |
A classifier learned by Adaboost and Haar-like feature is often used for detection of face-face parts. Although the dete... [more] | SDM2013-86 ICD2013-68 pp.111-116 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
A New Approach of the Analysis of the ISF in Oscillators with a Closed-Loop Control Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-97 |
The derivation of the impulse sensitivity function (ISF) of oscillators are widely used for the evaluation of the phase ... [more] | ICD2012-97 pp.37-40 |
| ICD | 2012-12-17 15:55 |
Tokyo | Tokyo Tech Front | [Poster Presentation]
Analysis of the Pull-in Range in a CDR-PLL with the Nonlinearity of the Phase Detector Shinji Shimizu, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2012-100 |
The analysis of the lock-in process of CDR-PLLs using the nonlinear model of the phase detector is presented. The analys... [more] | ICD2012-100 pp.45-48 |
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
The design of TDC and ADPLL circuits considering metastable operations Yasuyuki Shimizu (Osaka Inst. Tech.), Giichi Sakemi, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (OIT), Yoshio Matsuda (Kanazawa Univ.) ICD2011-104 |
[more] | ICD2011-104 pp.25-27 |
|
| ICD | 2011-12-15 16:10 |
Osaka | [Poster Presentation]
Simulation and Analysis of the Interference Noise between PLL circuits. Ken Maruhashi, Junki Mizuno, Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino (Osaka Inst. Tech.), Yoshio Matsuda (Kanazawa Univ.) ICD2011-110 |
When the multiple PLL circuits are laid out on a single IC chip, the influence of the interference between PLL circuits ... [more] | ICD2011-110 pp.57-58 |
|
[Return to Top Page]