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 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
MRIS, ITE-MMS 2013-07-12
15:45
Tokyo Chuo Univ. 3-Dimensional Phase Change Memory Enabling High Density and High Speed Storage
Takashi Kobayashi, Masaharu Kinoshita, Yoshitaka Sasago (Hitachi) MR2013-11
A three-dimensional vertical chain-cell-type phase change memory (VCCPCM) for next-generation large-capacity storage was... [more] MR2013-11
pp.31-34
ICD, SDM 2012-08-02
15:55
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes
Masaharu Kinoshita, Yoshitaka Sasago, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Yoshihisa Fujisaki, Shuichi Kusaba, Tadao Morimoto, Takashi Takahama, Toshiyuki Mine, Akio Shima, Yoshiki Yonamoto, Takashi Kobayashi (Hitachi) SDM2012-74 ICD2012-42
A three-dimensional (3-D) vertical chain-cell-type phase-change memory (VCCPCM) for next-generation large-capacity stora... [more] SDM2012-74 ICD2012-42
pp.59-63
SDM 2011-11-10
13:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Phase-change memoy driven by poly-Si transistor enabling three-dimensional stacking
Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi) SDM2011-117
A phase-change memory (PCM) driven by poly-Si MOS transistors was fabricated. The thin phase-change-material layer depos... [more] SDM2011-117
pp.11-15
SDM, ICD 2011-08-26
09:50
Toyama Toyama kenminkaikan Phase-change memory driven by poly-Si MOS transistor with low cost and high-programming throughput
Yoshitaka Sasago, Masaharu Kinoshita, Hiroyuki Minemura, Yumiko Anzai, Mitsuharu Tai, Kenzo Kurotsuchi, Seiichi Morita, Toshikazu Takahashi, Takashi Takahama, Tadao Morimoto, Toshiyuki Mine, Akio Shima, Takashi Kobayashi (Hitachi) SDM2011-85 ICD2011-53
A phase-change memory (PCM) driven by poly-Si MOS transistors was fabricated. The thin phase-change-material layer depos... [more] SDM2011-85 ICD2011-53
pp.75-78
ITE-MMS, MRIS 2009-10-09
10:25
Fukuoka FUKUOKA traffic center [Invited Talk] Low cost technology of phase change memory with low-contact-resistivity poly-Si selection diode
Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa, Toshiyuki Mine, Akio Shima, Yoshihisa Fujisaki, Hiroshi Moriya, Norikatsu Takaura, Kazuyoshi Torii (Hitachi) MR2009-26
We have fabricated the cross-point phase change memory with a selection diode made of poly-Si. The selection diode was f... [more] MR2009-26
pp.31-35
ICD, SDM 2009-07-17
12:00
Tokyo Tokyo Institute of Technology Cross-Point phase change memory with 4F2 cell size driven by low-contact resistivity poly-si diode
Yoshitaka Sasago, Masaharu Kinoshita, Takahiro Morikawa, Kenzo Kurotsuchi, Satoru Hanzawa, Toshiyuki Mine, Akio Shima, Yoshihisa Fujisaki, Hitoshi Kume, Hiroshi Moriya, Norikatsu Takaura, Kazuyoshi Torii (Hitachi) SDM2009-112 ICD2009-28
We have fabricated the cross-point phase change memory with a selection diode made of poly-Si. The selection diode was f... [more] SDM2009-112 ICD2009-28
pp.79-83
ICD, SDM 2006-08-18
15:25
Hokkaido Hokkaido University Impact of Random Telegraph Signals on Scaling of Multilevel Flash Memories
Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago (Hitachi), Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya (Renesas)
This paper describes for the first time the observation of the threshold voltage (Vth) fluctuation due to random telegra... [more] SDM2006-153 ICD2006-107
pp.161-166
ICD, SDM 2005-08-19
14:15
Hokkaido HAKODATE KOKUSAI HOTEL Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories
Kazuo Otsuga, Hideaki Kurata (Hitachi, Ltd.), Kenji Kozakai, Satoshi Noda (Renesas), Yoshitaka Sasago, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi (Hitachi, Ltd.)
We developed a selective-capacitance constant-charge-injection programming scheme for multilevel AG-AND flash memories. ... [more] SDM2005-153 ICD2005-92
pp.61-66
ICD 2005-04-14
16:15
Fukuoka   4Gb Multilevel AG-AND Flash Memory with 10MB/s Programming Throughput
Hideaki Kurata, Yoshitaka Sasago, Kazuo Otsuga, Tsuyoshi Arigane, Tetsufumi Kawamura, Takashi Kobayashi, Hitoshi Kume (Hitachi), Kazuki Homma, Kenji Kozakai, Satoshi Noda, Teruhiko Ito, Masahiro Shimizu, Yoshihiro Ikeda, Osamu Tsuchiya, Kazunori Furusawa (RENESAS)
We fabricated a 4Gb multilevel AG-AND flash memory using 90nm CMOS technology. By using an inversion-layer local-bitline... [more] ICD2005-11
pp.53-58
 Results 1 - 9 of 9  /   
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