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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
RECONF |
2014-06-12 10:50 |
Miyagi |
Katahira Sakura Hall |
An Asynchronous High-Performance FPGA Based on LEDR/Four-Phase-Dual-Rail Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2014-6 |
This paper presents an asynchronous high-performance FPGA that combines Four-Phase Dual-Rail (FPDR) protocol and Level-E... [more] |
RECONF2014-6 pp.27-30 |
RECONF |
2012-09-18 14:25 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
Area-Efficeint Design of Asynchronous Circuits Based on Balsa Framework for Synchronous FPGAs Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.) RECONF2012-30 |
[more] |
RECONF2012-30 pp.37-42 |
RECONF |
2012-09-18 14:50 |
Shiga |
Epock Ritsumei 21, Ritsumeikan Univ. |
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design Masanori Hariyama, Yoshiya Komatsu, Michitaka Kameyama (Tohoku Univ.) RECONF2012-31 |
[more] |
RECONF2012-31 pp.43-47 |
ICD, IPSJ-ARC |
2012-01-20 15:10 |
Tokyo |
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An Evaluation of An FPGA Based on Synchronous/Asynchronous Hybrid Architecture Yoshiya Komatsu, Masanori Hariyama, Shota Ishihara, Ryoto Tsuchiya, Michitaka Kameyama (Tohoku Univ.) ICD2011-142 |
This paper presents an FPGA architecture that combines synchronous and asynchronous architectures. Datapath components s... [more] |
ICD2011-142 pp.93-96 |
RECONF |
2010-09-17 10:15 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2010-33 |
Asynchronous circuit is power-efficient for low-workload sub-circuits since there is no power consumption of the clock t... [more] |
RECONF2010-33 pp.91-95 |
RECONF |
2009-09-18 13:35 |
Tochigi |
Utsunomiya Univ. |
An Asynchronous FPGA Using LEDR/4-Phase-Dual-Rail Protocol Converters Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) RECONF2009-36 |
This paper presents an asynchronous FPGA that combines the 4-phase dual-rail encoding and the Level-Encoded Dual-Rail (L... [more] |
RECONF2009-36 pp.103-108 |
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