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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 20  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2022-03-01
10:55
Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)
On Correction for Temperature and Voltage Effects in On-Chip Delay Measurement
Takaaki Kato (KIT), Yousuke Miyake (PRIVATECH), Seiji Kajihara (KIT) DC2021-67
It is effective for aging of a logic circuit to measure a circuit delay periodically in field. In order to compare the d... [more] DC2021-67
pp.18-23
DC 2020-12-11
13:00
Hyogo
(Primary: On-site, Secondary: Online)
A Degradation Prediction of Circuit Delay Using A Gradient Descent Method
Seiichirou Mori, Masayuki Gondou, Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech) DC2020-59
As the risk of aging-induced faults of VLSIs is increasing, highly reliable systems require to predict when the aging-in... [more] DC2020-59
pp.1-6
DC 2020-02-26
10:00
Tokyo   On Machine Learning Based Accuracy Improvement for A Digital Temperature and Voltage Sensor
Masayuki Gondo, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2019-86
To measure an on-chip temperature and voltage during VLSI operation, an RO(Ring Oscillator)-based digital temperature an... [more] DC2019-86
pp.1-6
DC 2019-12-20
16:30
Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
DC 2018-12-14
13:00
Okinawa Miyako Seisyonen-No-Ie On-Chip Delay Measurement for In-field Periodic Test of FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2018-58
Delay-related failures due to aging phenomena are a critical issue of state-of-the-art VLSI systems. In order to detect ... [more] DC2018-58
pp.1-6
DC 2018-02-20
15:05
Tokyo Kikai-Shinko-Kaikan Bldg. A method for improving an estimation accuracy of a specific temperature and voltage range in a digital temperature and voltage sensor
Kenji Inoue, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2017-85
An RO(Ring Oscillator)-based digital temperature and voltage sensor has been proposed in order to measure an on-chip tem... [more] DC2017-85
pp.49-54
DC 2017-12-15
15:30
Akita Akita Study Center, The Open University of Japan A Test Clock Observation Method Using Time-to-Digital Converters for Built-In Self-Test in FPGAs
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) DC2017-75
A delay measurement method combining a logic BIST with a variable test clock has been proposed to improve field reliabil... [more] DC2017-75
pp.37-42
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2017-07-26
16:15
Akita Akita Atorion-Building (Akita) A Two-Temperature-Point Calibration Method for A Digital Temperature And Voltage Sensor
Yousuke Miyake, Yasuo Sato, Seiji kajihara (KIT) DC2017-19
A measurement method of a digital sensor using ring oscillators to measure a temperature and a voltage of a VLSI was pro... [more] DC2017-19
pp.19-24
DC 2015-12-18
13:20
Niigata Kurieito Mulakami (Murakami City) On Measurement of On-Chip Temperature And Voltage Variation Using A Digital Monitor
Yousuke Miyake, Takaaki Kato, Takuya Itonaga, Yasuo Sato, Seiji Kajihara (KIT) DC2015-74
A digital monitor for measuring a temperature and a voltage of VLSIs is proposed. The monitor can derive measurement res... [more] DC2015-74
pp.5-10
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
10:50
Nagasaki Nagasaki Kinro Fukushi Kaikan On Correction of Temperature Influence to Delay Measurement in FPGAs
Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT) VLD2015-63 DC2015-59
As a means for delay testing for VLSIs in field, a measurement method of a path delay for a logic circuit using variable... [more] VLD2015-63 DC2015-59
pp.165-170
DC 2014-12-19
13:00
Toyama   Study on reduction and control of NBTI-induced degradation in FPGA-based ring oscillators
Yasuo Sato, Yousuke Miyake, Seiji Kajihara (Kyutech) DC2014-67
Ring oscillators are used for variety of applications to enhance reliability on LSIs or FPGAs; however, the performance ... [more] DC2014-67
pp.1-6
DC 2014-12-19
13:25
Toyama   A Temperature Monitor Using Ring-Oscillators on FPGA
Yousuke Miyake, Yasuo Sato, Seiji Kajihara (kyutech) DC2014-68
On-chip temperature monitors are often used to guarantee the reliability of VLSIs and monitors using ring oscillators ha... [more] DC2014-68
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
14:45
Oita B-ConPlaza On-chip delay measurement for FPGAs
Kentaro Abe, Yousuke Miyake, Seiji Kajihara, Yasuo Sato (KIT) VLD2014-109 DC2014-63
This paper describes an on-chip delay measurement method that targets a logic circuit on an FPGA. While advances in semi... [more] VLD2014-109 DC2014-63
pp.245-250
DC 2013-12-13
13:25
Ishikawa   Variable Test-Timing Generation for Built-In Self-Test on FPGA
Yasuo Sato, Munehiro Matsuura, Hitoshi Arakawa, Yousuke Miyake, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-69
This paper proposes a variable test-timing generation method that should be used for built-in self-test on FPGA. Applica... [more] DC2013-69
pp.7-12
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-28
13:45
Kagoshima   A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs
Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.) VLD2013-84 DC2013-50
FPGAs are used in various embedded systems including highly reliable systems, therefore, it is important to ensure its r... [more] VLD2013-84 DC2013-50
pp.165-170
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2013-11-29
09:20
Kagoshima   Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) VLD2013-93 DC2013-59
Power reduction during Logic BIST is a crucial problem; however, power controlling technologies are required as well as ... [more] VLD2013-93 DC2013-59
pp.233-238
DC 2013-02-13
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. Temperature and voltage estimation considering manufacturing variability for a monitoring circuit
Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.) DC2012-89
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, a highly accur... [more] DC2012-89
pp.55-60
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
14:30
Fukuoka Centennial Hall Kyushu University School of Medicine Design of temperature and voltage monitoring circuit structure for field test
Wataru Tsumori, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT), Yukiya Miura (TMU) VLD2012-101 DC2012-67
For improving reliability of LSIs, the delay increase caused by aging during system operation should be detected before ... [more] VLD2012-101 DC2012-67
pp.243-248
DC 2012-06-22
16:35
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg Evaluation of the on-chip temperature and voltage using ring-oscillator-based monitoring circuit and a study for an application to field test
Yousuke Miyake, Takuma Sasakawa, Yasuo Sato, Seiji Kajihara (Kyutech), Yukiya Miura (TMU) DC2012-16
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, highly accurat... [more] DC2012-16
pp.45-50
DC 2012-02-13
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. Evaluation of a thermal and voltage estimation circuit for field test
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) DC2011-86
High dependability is required for an embedded system VLSI. High functionality and high performance of VLSI, due to the ... [more] DC2011-86
pp.61-66
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