IEICE Technical Committee Submission System
Conference Schedule		 Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 5 of 5  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICTSSL 2018-07-17
13:50		 Tokyo NTT Musashino R&D Center Proposal of Individual Hazard-Map Utilizing Personalized Video Technology -- Project of "Understanding Individual Hazard-Map for My Housing by Video" --
Munenari Inoguchi (Univ. of Toyama), Eiichi Mano (Tanoshi Chiribiz Co.), Ryu Kurihara, Yuji Osaki (NTT DATA CCS Co.) ICTSSL2018-18		 Recently we were affected by many kinds of disaster, such as Earthquake, Tsunami, Flood, Land-slide and so on. In charge... [more] ICTSSL2018-18
pp.13-16
ICD, ITE-IST 2011-07-21
09:30		 Hiroshima Hiroshima Institute of Technology A Level Shifter with Logic Error Correction Circuit for Low-Voltage Digital LSIs
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2011-21		 A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit consists of a le... [more] ICD2011-21
pp.1-6
ICD, ITE-IST 2011-07-21
09:55		 Hiroshima Hiroshima Institute of Technology A Sense Amplifier with High Speed Pre-Charge Operation for Ultra-Low-Voltage SRAM
Chotaro Masuda, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa (Kove Univ.) ICD2011-22		 We propose a current latch sense amplifier with
a current-reuse technique (CLSA-w/CR). The CLSA-w/CR is
capable of hig... [more]		 ICD2011-22
pp.7-12
ICD, ITE-IST 2010-07-23
17:25		 Osaka Josho Gakuen Osaka Center Level Converter Circuit for Low Voltage Digital LSIs
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2010-38		 Supply voltage scaling in accordance with device scaling has achieved low power dissipation of CMOS LSIs. Because each c... [more] ICD2010-38
pp.133-138
ICD, ITE-IST 2009-10-02
17:50		 Tokyo CIC Tokyo (Tamachi) Delay Variation Tolerant Subthreshold Digital Circuits for Ultra-Low Power
Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) ICD2009-62		 Subthreshold LSIs can achieve ultra-low power. However, threshold voltage variations with temperature and fabrication pr... [more] ICD2009-62
pp.165-170
 Results 1 - 5 of 5  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

[Return to Top Page]

[Return to IEICE Web Page]
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan