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VLD, HWS [detail] 2022-03-07
09:35		 Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54		 Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
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