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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 53  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS, ICD 2024-03-01
09:20
Okinawa
(Primary: On-site, Secondary: Online)

Kei Nakao, Yukihide Kohira, Hiroshi Saito, Yoichi Tomioka (Univ. of Aizu) VLD2023-120 HWS2023-80 ICD2023-109
(To be available after the conference date) [more] VLD2023-120 HWS2023-80 ICD2023-109
pp.107-112
VLD, HWS, ICD 2024-03-01
09:45
Okinawa
(Primary: On-site, Secondary: Online)
VLD2023-121 HWS2023-81 ICD2023-110 (To be available after the conference date) [more] VLD2023-121 HWS2023-81 ICD2023-110
pp.113-118
VLD, HWS, ICD 2024-03-01
10:10
Okinawa
(Primary: On-site, Secondary: Online)
Fault Detectable Convolutional Neural Network Circuits With Dual Modular Redundancy Based on Mixed-precision Quantization
Yamato Saikawa, Yuta Owada, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira (UoA) VLD2023-122 HWS2023-82 ICD2023-111
In safety-critical edge AI systems, circuit failures caused by aging or cosmic ray can lead to serious accidents. Dual M... [more] VLD2023-122 HWS2023-82 ICD2023-111
pp.119-124
HWS, VLD 2023-03-01
14:55
Okinawa
(Primary: On-site, Secondary: Online)
High fidelity mask pattern generation method by amplitude component evaluation
Yu Horimoto, Sota Saito, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-79 HWS2022-50
 [more] VLD2022-79 HWS2022-50
pp.37-42
HWS, VLD 2023-03-01
15:20
Okinawa
(Primary: On-site, Secondary: Online)
A fast SRAF optimization using Voronoi diagram and LUT based intensity evaluation
Sota Saito, Yu Horimoto, Atsushi Takahashi (Tokyo Tech), Yukihide Kohira (Univ. of Aizu), Chikaaki Kodama (KIOXIA) VLD2022-80 HWS2022-51
Recent advances in technology nodes have led to problems in optical lithography such as reduced fidelity of transferred ... [more] VLD2022-80 HWS2022-51
pp.43-48
HWS, VLD 2023-03-02
09:30
Okinawa
(Primary: On-site, Secondary: Online)
VLD2022-85 HWS2022-56 (To be available after the conference date) [more] VLD2022-85 HWS2022-56
pp.73-78
HWS, VLD 2023-03-03
11:00
Okinawa
(Primary: On-site, Secondary: Online)

Yusei Yano, Shinji Nozaki, Tomohide Aizawa, Yukihide Kohira (Univ. of Aizu) VLD2022-103 HWS2022-74
(To be available after the conference date) [more] VLD2022-103 HWS2022-74
pp.161-166
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
10:45
Kumamoto  
(Primary: On-site, Secondary: Online)
Mask Optimization Using Voronoi Partition and Iterative Improvement
Naoki Nonaka, Yukihide Kohira (Univ. of Aizu), Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64
To realize continuously scaling down technology node, progressing manufacturing process by optical lithography is requir... [more] VLD2022-41 ICD2022-58 DC2022-57 RECONF2022-64
pp.127-132
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-02
15:35
Online Online Mask Optimization Method Using Simulated Quantum Annealing
Yukihide Kohira, Haruki Nakayama, Naoki Nonaka (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA Corporation) VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
To realize continuously scaling down of technology node, progressing manufacturing process by optical lithography is req... [more] VLD2021-45 ICD2021-55 DC2021-51 RECONF2021-53
pp.162-167
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2020-11-18
09:55
Online Online Seat Layout Method Considering Physical Distance Using Cell Placement Methods in LSI
Yukihide Kohira (Univ. of Aizu) VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53
Due to the spread of COVID-19 infection, it is required to secure a physical distance between people. In this paper, the... [more] VLD2020-34 ICD2020-54 DC2020-54 RECONF2020-53
pp.127-131
HWS, VLD [detail] 2020-03-04
14:55
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Gate Sizing for Programmable Delay Elements on Post-Silicon Delay Tuning
Kota Muroi, Yukihide Kohira (UoA) VLD2019-103 HWS2019-76
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] VLD2019-103 HWS2019-76
pp.53-58
HWS, VLD [detail] 2020-03-04
16:00
Okinawa Okinawa Ken Seinen Kaikan
(Cancelled but technical report was issued)
Pixel-based Mask Optimization with Lagrangian Relaxation and Boundary Flipping
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-105 HWS2019-78
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-105 HWS2019-78
pp.65-70
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
16:35
Ehime Ehime Prefecture Gender Equality Center Mask Optimization Considering Process Variation by Subgradient Method
Yukihide Kohira, Rina Azuma (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama (KIOXIA) VLD2019-53 DC2019-77
Due to miniaturization of process technology, progressing manufacturing process by optical lithography is required. In r... [more] VLD2019-53 DC2019-77
pp.197-202
HWS, VLD 2019-02-27
15:20
Okinawa Okinawa Ken Seinen Kaikan Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework
Masataka Aoki, Yukihide Kohira (Univ. of Aizu) VLD2018-102 HWS2018-65
In general-synchronous framework (g-frame), in which a clock is not assumed to be distributed to all registers simultane... [more] VLD2018-102 HWS2018-65
pp.55-60
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
14:10
Hiroshima Satellite Campus Hiroshima Process Variation-aware Model-based OPC using 0-1 Quadratic Programming
Rina Azuma, Yukihide Kohira (Univ. of Aizu), Tomomi Matsui, Atsushi Takahashi (Tokyo Tech), Chikaaki Kodama, Shigeki Nojima (TMC) VLD2018-70 DC2018-56
Due to continuous shrinking of Critical Dimensions (CD) of layout pattern in VLSI, advances of manufacturing process in ... [more] VLD2018-70 DC2018-56
pp.209-214
CAS, SIP, MSS, VLD 2018-06-14
16:15
Hokkaido Hokkaido Univ. (Frontier Research in Applied Sciences Build.) Acceleration of Analytical Placement by Wire Length Prediction using Machine Learning
Tatsuki Hoshiba, Yukihide Kohira (Univ. of Aizu) CAS2018-14 VLD2018-17 SIP2018-34 MSS2018-14
In recent LSI design, it is difficult to obtain a placement that satisfies both design constraints and specifications du... [more] CAS2018-14 VLD2018-17 SIP2018-34 MSS2018-14
pp.75-80
VLD, IPSJ-SLDM 2018-05-16
15:50
Fukuoka Kitakyushu International Conference Center Pixel-based OPC using Quadratic Programming for Mask Optimization
Rina Azuma, Yukihide Kohira (Univ. of Aizu) VLD2018-3
Due to continuous shrinking of Critical Dimensions (CD) in semiconductor manufacturing, advance of process technology in... [more] VLD2018-3
pp.31-36
VLD, HWS
(Joint)
2018-03-01
09:50
Okinawa Okinawa Seinen Kaikan Clustering for Reduction of Power Consumption and Area on Post-Silicon Delay Tuning
Kota Muroi, Yukihide Kohira (Univ. of Aizu) VLD2017-107
Due to progressing process technology, yield of chips is reduced by timing violation caused by delay variation of gates ... [more] VLD2017-107
pp.109-114
VLD 2017-03-01
14:50
Okinawa Okinawa Seinen Kaikan Post-Silicon Delay Tuning Method for Power Reduction considering Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-104
Due to the progress of the process technology in LSI, the yield of chips is reduced by the timing violation because of t... [more] VLD2016-104
pp.13-18
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
13:35
Osaka Ritsumeikan University, Osaka Ibaraki Campus Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA
Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu) VLD2016-48 DC2016-42
Recently, the logic circuits are implemented to FPGA in many fields.
To achieve faster circuits, a design flow to imple... [more]
VLD2016-48 DC2016-42
pp.25-30
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