| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, RECONF | 2025-01-16 10:30 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
 VLD2024-79 RECONF2024-109 |
(To be available after the conference date) [more] | VLD2024-79 RECONF2024-109 pp.18-22 |
| DC, CPSY, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2024-03-23 10:15 |
Nagasaki | Ikinoshima Hall (Nagasaki, Online) (Primary: On-site, Secondary: Online) |
Itsuki Nakai (TUT), Takaaki Fukai, Takahiro Hirofuchi (AIST), Yukinori Sato (TUT) CPSY2023-50 DC2023-116 |
(To be available after the conference date) [more] | CPSY2023-50 DC2023-116 pp.71-76 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 16:20 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Interface development for Python use of FPGA cluster ESSPER Taiki Watanabe (TUT), Kentaro Sano (R-CCS), Yukinori Sato (TUT) VLD2022-62 RECONF2022-85 |
[more] | VLD2022-62 RECONF2022-85 pp.27-28 |
| RECONF | 2022-09-07 14:10 |
Aichi | emCAMPUS STUDIO (Aichi, Online) (Primary: On-site, Secondary: Online) |
Efficient Learning of Spiking Neural Networks with Genetic Algorithm and its FPGA Acceleration Taiki Watanabe, Yukinori Sato (TUT) RECONF2022-26 |
Spiking Neural Network (SNN) is one of the promising models of neuromorphic architecture. A learning method using a gene... [more] | RECONF2022-26 pp.1-6 |
| RECONF | 2021-09-10 14:10 |
Online | Online (Online) | RECONF2021-20 |
[more] | RECONF2021-20 pp.19-23 |
| RECONF | 2019-05-10 11:15 |
Tokyo | Tokyo Tech Front (Tokyo) | A case study of system development based on software hardware co-design using an FPGA/CPU mixed SoC
-- Implementation of the Julia set explorer using Ultra96 -- Kenta Sato, Yukinori Sato (TUT) RECONF2019-13 |
(To be available after the conference date) [more] | RECONF2019-13 pp.67-72 |
| RECONF, CPSY, DC, IPSJ-ARC (Joint) [detail] |
2017-05-23 10:15 |
Hokkaido | Noboribetsu-Onsen Dai-ichi-Takimoto-Kan (Hokkaido) | RECONF2017-14 |
(To be available after the conference date) [more] | RECONF2017-14 pp.69-73 |
| CPM, LQE, ED | 2016-12-13 14:40 |
Kyoto | Kyoto University (Kyoto) | Characterization of electric properties for wide-gap semiconductors using terahertz time-domain elipsometry Takashi Fujii (RITS/PNP), Kohei Tachi, Tsutomu Araki, Yasushi Nanishi (RITS), Toshiyuki Iwamoto, Yukinori Sato (PNP), Takshi Nagashima (Setsunan Univ.) ED2016-78 CPM2016-111 LQE2016-94 |
Scattering time () of several inorganic semiconductors are around 10-1 psec. Therefore, electric properties, suc... [more] | ED2016-78 CPM2016-111 LQE2016-94 pp.103-106 |
| CPSY, IPSJ-ARC | 2015-10-08 10:00 |
Chiba | Makuhari-messe (Chiba) | [Technology Exhibit]
Demonstration of an application analysis tool "Exana" for assisting CPU performance tuning Yukinori Sato, Shimpei Sato, Toshio Endo (Tokyo Tech) CPSY2015-48 |
We have been developing Exana tool set that can transparently analyze application code execution at run time using pre-c... [more] | CPSY2015-48 pp.11-13 |
| RECONF | 2013-09-19 11:25 |
Ishikawa | Japan Advanced Institute of Science and Technology (Ishikawa) | A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2013-31 |
[more] | RECONF2013-31 pp.67-72 |
| RECONF | 2011-09-27 09:25 |
Aichi | Nagoya Univ. (Aichi) | A Design Framework for relieving a HW Bottleneck FPGAs Connected with a High-Speed Data Bus Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2011-33 |
As reconfigurable devices with a PCI-Express interface appear in the market, the data transfer speed between the reconfi... [more] | RECONF2011-33 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-12-01 10:45 |
Fukuoka | Kyushu University (Fukuoka) | An Effective Processing Method for Parallel Loops on FPGA with PCI-Express Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST) RECONF2010-47 |
As FPGAs with a PCI-Express Interface appear in the market, the data transter speed between FPGA and other units, such a... [more] | RECONF2010-47 pp.49-54 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2008-11-17 14:15 |
Fukuoka | Kitakyushu Science and Research Park (Fukuoka) | A Method of Processing Data-Parallel Tasks on Multi-Context Reconfigurable Processor Koichi Araki, Yukinori Sato, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology) RECONF2008-41 |
A Multi-context Reconfigurable Processor (MRP) can treat various tasks with hardware. However, in the case of treating a... [more] | RECONF2008-41 pp.15-20 |
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