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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 23  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2021-02-05
10:30
Online Online A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) DC2020-69
FPGAs are integrated circuits that can be implemented arbitrary logic functions. In FPGAs, it is important to measure pr... [more] DC2020-69
pp.1-6
DC 2020-02-26
15:45
Tokyo   Frequency Variation of Ring Oscillators During Long-Time Operation on FPGA
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-95
FPGAs (Field Programmable Gate Arrays) are integrated circuits that can be implemented arbitrary logic functions by reco... [more] DC2019-95
pp.55-60
DC 2020-02-26
16:35
Tokyo   Soft Error Tolerance of Power-Supply-Noise Hardened Latches
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-97
In recent years, with the scaling down and low-power operation of VLSI circuits, reliability degradation due to soft err... [more] DC2019-97
pp.67-72
DC 2019-12-20
16:30
Wakayama   Aging Observation using On-Chip Delay Measurement in Long-term Reliability Test
Yousuke Miyake, Takaaki Kato, Seiji Kajihara (Kyutech), Masao Aso, Haruji Futami, Satoshi Matsunaga (Syswave), Yukiya Miura (TMU) DC2019-85
Avoidance of delay-related faults due to aging phenomena is an important issue of VLSI systems. Periodical delay measure... [more] DC2019-85
pp.37-42
DC 2019-02-27
15:35
Tokyo Kikai-Shinko-Kaikan Bldg. Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2018-82
With the scaling down and low-power operation of VLSI circuits, influence on circuit behavior by power supply noise such... [more] DC2018-82
pp.67-72
DC 2018-02-20
15:30
Tokyo Kikai-Shinko-Kaikan Bldg. Investigation of a Measurement Method of Characteristic Variations in the FPGA Considering an LUT Structure
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-86
FPGAs (Field Programmable Gate Arrays) are integrated circuits that can implement arbitrary logic functions by reconfigu... [more] DC2017-86
pp.55-60
DC 2018-02-20
16:35
Tokyo Kikai-Shinko-Kaikan Bldg. Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures
Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-88
With the scaling down and low power operation of VLSI circuits, effects on circuit behavior by power supply noise such a... [more] DC2017-88
pp.67-72
DC 2017-02-21
16:10
Tokyo Kikai-Shinko-Kaikan Bldg. Considerations on Characteristics of Ring Oscillators Implemented in FPGA
Kouhei Satou, Yukiya Miura (Tokyo Metropolitan Univ.) DC2016-82
FPGAs (Field Programmalbe Gate Arrays) are integrated circuits that can be implemented arbitrary logic functions by reco... [more] DC2016-82
pp.45-52
DC 2016-02-17
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96
According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the o... [more] DC2015-96
pp.61-66
DC 2014-06-20
13:15
Tokyo Kikai-Shinko-Kaikan Bldg. Development of a delay time measurement circuit by inserting buffers
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2014-10
According to the scaling down, lower power design, and highly operational frequency of the device, the process variabili... [more] DC2014-10
pp.1-6
DC 2014-06-20
13:40
Tokyo Kikai-Shinko-Kaikan Bldg. A method of LSI degradation estimation using ring oscillators
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.) DC2014-11
Aging called Negative Bias Temperature Instability (NBTI), Negative Bias Temperature Instability (NBTI) and Chanel Hot C... [more] DC2014-11
pp.7-14
DC 2013-06-21
16:30
Tokyo Kikai-Shinko-Kaikan Bldg. A Method of Transistor Degradation Estimation Using Ring Oscillators
Tatsunori Ikeda, Yukiya Miura (Tokyo Metropolitan Univ.) DC2013-15
Aging called Negative Bias Temperature Instability (NBTI), Negative Bias Temperature Instability (NBTI) and Chanel Hot C... [more] DC2013-15
pp.31-36
DC 2013-02-13
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. Temperature and voltage estimation considering manufacturing variability for a monitoring circuit
Yousuke Miyake, Wataru Tsumori, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yukiya Miura (Tokyo Metropolitan Univ.) DC2012-89
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, a highly accur... [more] DC2012-89
pp.55-60
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
14:30
Fukuoka Centennial Hall Kyushu University School of Medicine Design of temperature and voltage monitoring circuit structure for field test
Wataru Tsumori, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (KIT), Yukiya Miura (TMU) VLD2012-101 DC2012-67
For improving reliability of LSIs, the delay increase caused by aging during system operation should be detected before ... [more] VLD2012-101 DC2012-67
pp.243-248
DC 2012-06-22
16:35
Tokyo Room B3-1 Kikai-Shinko-Kaikan Bldg Evaluation of the on-chip temperature and voltage using ring-oscillator-based monitoring circuit and a study for an application to field test
Yousuke Miyake, Takuma Sasakawa, Yasuo Sato, Seiji Kajihara (Kyutech), Yukiya Miura (TMU) DC2012-16
Delay increase due to aging phenomena is a critical issue of VLSIs. For detecting such increase in field, highly accurat... [more] DC2012-16
pp.45-50
DC 2012-02-13
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. Design of Dual Edge Triggered Flip-Flops and Application to Signal Delay Detection
Yoshihiro Ohkawa, Yukiya Miura (TMU) DC2011-76
Conventional edge triggered flip-flops sample a data signal synchronizing with single clock edge. If a noise signal occu... [more] DC2011-76
pp.1-6
DC 2012-02-13
16:20
Tokyo Kikai-Shinko-Kaikan Bldg. Evaluation of a thermal and voltage estimation circuit for field test
Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Kohei Miyase (Kyutech), Yukiya Miura (TMU) DC2011-86
High dependability is required for an embedded system VLSI. High functionality and high performance of VLSI, due to the ... [more] DC2011-86
pp.61-66
DC 2011-02-14
15:40
Tokyo Kikai-Shinko-Kaikan Bldg. Dual Edge Triggered Flip-Flops for Blocking Noise Pulses on Data Signal Lines
Yukiya Miura (Tokyo Metropolitan Univ.) DC2010-68
This paper proposes a new flip-flop design, a dual edge triggered flip-flops, for dependable design taking into account ... [more] DC2010-68
pp.57-62
ICD
(Workshop)
2010-08-16
- 2010-08-18
Overseas Ho Chi Minh City University of Technology [Invited Talk] Circuit Failure Prediction by Field Test (DART) with Delay-Shift Measurement Mechanism
Yasuo Sato, Seiji Kajihara (Kyusyu Institute of Technology), Michiko Inoue, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara (NAIST), Yukiya Miura (Tokyo Metropolitan Univ.)
The main task of test had traditionally been screening of hard defects before shipping. However, current chips are takin... [more]
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2009-12-04
14:25
Kochi Kochi City Culture-Plaza A Path Selection Method of Delay Test for Transistor Aging
Mitsumasa Noda (Kyushu Institute of Tech.), Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen (Kyushu Institute of Tech./JST), Yukiya Miura (Tokyo Metropolitan Univ./JST) VLD2009-65 DC2009-52
With the advanced VLSI process technology, it is important for reliability of VLSIs to deal with faults caused by aging.... [more] VLD2009-65 DC2009-52
pp.167-172
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