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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-26 14:15 |
Online | Online (Online) | A new method for evaluating corruption metric and resilience of logic locking Shusaku Minami, Yusuke Matsunaga (Kyushu Univ.)  VLD2020-63 CPSY2020-46 RECONF2020-82 |
[more] | VLD2020-63 CPSY2020-46 RECONF2020-82 pp.137-142 |
| HWS, VLD [detail] | 2020-03-06 14:55 |
Okinawa | Okinawa Ken Seinen Kaikan (Okinawa) (Cancelled but technical report was issued) |
On evaluation of logic locking method based on Affine transformation Yusuke Matsunaga (Kyushu Univ.) VLD2019-132 HWS2019-105 |
[more] | VLD2019-132 HWS2019-105 pp.221-225 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-22 16:15 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Kanagawa) | On logic locking method with affine transformation Yusuke Matsunaga (Kyushu Univ.) VLD2019-63 CPSY2019-61 RECONF2019-53 |
[more] | VLD2019-63 CPSY2019-61 RECONF2019-53 pp.55-59 |
| MSS, CAS, SIP, VLD | 2019-07-30 16:15 |
Iwate | Iwate Univ. (Iwate) | [Panel Discussion]
The role of System and Signal Processing Subsociety
-- Offering Effective Information of Research Groups and The Subsociety -- Yusuke Matsunaga (Kyushu Univ.), Taizo Yamawaki (Hitachi), Nozomu Togawa (Waseda Univ.), Naoyuki Aikawa (Tokyo Univ. of Science), Shigemasa Takai (Osaka Univ.) CAS2019-10 VLD2019-16 SIP2019-26 MSS2019-10 |
[more] | CAS2019-10 VLD2019-16 SIP2019-26 MSS2019-10 p.41 |
| HWS, VLD | 2019-03-01 12:40 |
Okinawa | Okinawa Ken Seinen Kaikan (Okinawa) | On evaluation of an efficient SAT attack algorithm for logic encryption Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.) VLD2018-126 HWS2018-89 |
[more] | VLD2018-126 HWS2018-89 pp.199-204 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-06 13:00 |
Hiroshima | Satellite Campus Hiroshima (Hiroshima) | An efficient SAT-attack algorithm against logic encryption Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2018-60 DC2018-46 |
[more] | VLD2018-60 DC2018-46 pp.143-148 |
| VLD, HWS (Joint) |
2018-03-01 10:55 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Implementation and Evaluation of MCTS-Based Parallel Prefix Adder Synthesis Taeko Matsunaga (NBU), Yusuke Matsunaga (Kyushu Univ.) |
[more] | |
| VLD, HWS (Joint) |
2018-03-01 13:50 |
Okinawa | Okinawa Seinen Kaikan (Okinawa) | Evaluating logic encryption methods using error correcting logic synthesis Yusuke Matsunaga (Kyushu Univ.) VLD2017-112 |
[more] | VLD2017-112 pp.139-144 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2017-11-07 09:50 |
Kumamoto | Kumamoto-Kenminkouryukan Parea (Kumamoto) | On low power oriented test pattern compaction using SAT solver Yusuke Matsunaga (Kyushu Univ.) VLD2017-43 DC2017-49 |
This paper proposes a test pattern compaction method under power consumption constraint, which uses SAT solver based ... [more] |
VLD2017-43 DC2017-49 pp.95-99 |
| SIP, CAS, MSS, VLD | 2017-06-20 14:50 |
Niigata | Niigata University, Ikarashi Campus (Niigata) | SAT model sampling for test pattern generation considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
CAS2017-21 VLD2017-24 SIP2017-45 MSS2017-21 pp.107-112 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 09:50 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus (Osaka) | On SAT based test pattern generation for transition faults considering signal activities Yusuke Matsunaga (Kyushu Univ.) VLD2016-63 DC2016-57 |
This paper presents a test pattern generation method with considering signal transition activities using a SAT solver... [more] |
VLD2016-63 DC2016-57 pp.111-115 |
| VLD, CAS, MSS, SIP | 2016-06-16 10:30 |
Aomori | Hirosaki Shiritsu Kanko-kan (Aomori) | On random test pattern generation algorithm considering signal transition activities Yusuke Matsunaga (Kyushu Univ.) CAS2016-4 VLD2016-10 SIP2016-38 MSS2016-4 |
This paper presents a test pattern generation method with considering signal transition activities using Markov chain... [more] |
CAS2016-4 VLD2016-10 SIP2016-38 MSS2016-4 pp.19-22 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-02 11:40 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan (Nagasaki) | On applications of Monte-Carlo tree search algorithm for CAD problems Yusuke Matsunaga (Kyushu Univ.) VLD2015-46 DC2015-42 |
[more] | VLD2015-46 DC2015-42 pp.51-55 |
| MSS, CAS, SIP, VLD | 2015-06-17 11:10 |
Hokkaido | Otaru University of Commerce (Hokkaido) | Accelerating techniques for test pattern compaction for large circuits Yusuke Matsunaga (Kyushu Univ.) CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5 |
This paper presents accelerating techniques for test pattern compaction algorithm applicable for large scale circuits.... [more] |
CAS2015-5 VLD2015-12 SIP2015-36 MSS2015-5 pp.25-30 |
| MSS, CAS, SIP, VLD | 2015-06-17 16:20 |
Hokkaido | Otaru University of Commerce (Hokkaido) | [Panel Discussion]
The Role of System and Signal Processing Subsociety
-- Society Activity and Job Search -- Atsushi Takahashi (Tokyo Tech), Yoshihiro Kaneko (Gifu Univ.), Yusuke Matsunaga (Kyushu Univ.), Osamu Hoshuyama, Yuichi Nakamura (NEC) CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 |
The four technical committees of System and Signal Processing Subsociety have been holding joint workshop since 2010. We... [more] | CAS2015-12 VLD2015-19 SIP2015-43 MSS2015-12 p.65 |
| VLD, IPSJ-SLDM | 2015-05-14 09:15 |
Fukuoka | Kitakyushu International Conference Center (Fukuoka) | A minimum test pattern set generation for large circuits Yusuke Matsunaga (Kyushu Univ.) VLD2015-1 |
[more] | VLD2015-1 pp.1-6 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:50 |
Oita | B-ConPlaza (Oita) | On implicit enumeration of vector pairs for synthesizing index generator Yusuke Matsunaga (Kyushu Univ.) VLD2014-95 DC2014-49 |
[more] | VLD2014-95 DC2014-49 pp.161-165 |
| IE, ICD, VLD, IPSJ-SLDM [detail] | 2014-10-02 13:00 |
Miyagi | (Miyagi) | Logic Synthesis of Linear Transformation Circuit for Parallel Index Generator Yusuke Matsunaga (Kyushu Univ.) VLD2014-60 ICD2014-53 IE2014-39 |
[more] | VLD2014-60 ICD2014-53 IE2014-39 pp.1-6 |
| CAS, SIP, MSS, VLD, SIS [detail] | 2014-07-11 13:00 |
Hokkaido | Hokkaido University (Hokkaido) | Accelerating Boolean Matching of LUT-based Circuits using CEGAR method Yusuke Matsunaga (Kyushu Univ.) CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 |
This paper describes an accelerating technique for Boolean matching of LUT-based circuits, which is based on CEGAR (coun... [more] | CAS2014-38 VLD2014-47 SIP2014-59 MSS2014-38 SIS2014-38 pp.201-206 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-29 13:45 |
Kanagawa | Hiyoshi Campus, Keio University (Kanagawa) | On Boolean Matching of LUT-based Circuits Yusuke Matsunaga (Kyushu Univ.) VLD2013-127 CPSY2013-98 RECONF2013-81 |
This paper describes two speed-up techniques for Boolean matching of LUT-based circuits. One is one-hot encoding tec... [more] |
VLD2013-127 CPSY2013-98 RECONF2013-81 pp.149-154 |
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