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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
Online Online [Invited Talk] Analog in-memory computing in FeFET based 1T1R array for low-power edge AI applications
Daisuke Saito, Toshiyuki Kobayashi, Hiroki Koga (SONY), Yusuke Shuto, Jun Okuno, Kenta Konishi (SSS), Masanori Tsukamoto, Kazunobu Ohkuri (SONY), Taku Umebayashi (SSS), Takayuki Ezaki (SONY) SDM2021-36 ICD2021-7
Deep neural network (DNN) inference for edge AI requires low-power operation, which can be achieved by implementing mass... [more] SDM2021-36 ICD2021-7
ICD, SDM, ITE-IST [detail] 2020-08-06
Online Online [Invited Talk] SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2 -- Report on 2020 IEEE VLSI Symposia --
Jun Okuno, Takafumi Kunihiro, Kenta Konishi, Fumitaka Sugaya, Yusuke Shuto, Hideki Maemura, Masanori Tsukamoto, Taku Umebayashi (SSS) SDM2020-1 ICD2020-1
 [more] SDM2020-1 ICD2020-1
(Joint) [detail]
Kumamoto Kumamoto City International Center
Takeharu Ikezoe, Hideharu Amano (Keio Univ.), Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) CPSY2018-32
 [more] CPSY2018-32
Okinawa Okinawa Seinen Kaikan Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data
Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] VLD2017-122
ICD 2017-04-21
Tokyo   [Invited Lecture] Architectures and energy performance of nonvolatile SRAM for core-level nonvolatile power-gating
Daiki Kitagata, Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. of Tech.) ICD2017-10
Architectures and energy performance of nonvolatile SRAM (NV-SRAM) are demonstrated for nonvolatile power-gating (NVPG) ... [more] ICD2017-10
ICD, SDM 2012-08-02
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido Static noise margin and energy performance analyses of a nonvolatile SRAM cell using pseudo-spin-MOSFET
Yusuke Shuto, Shuu'ichirou Yamamoto, Satoshi Sugahara (Tokyo Inst. Tech.) SDM2012-75 ICD2012-43
 [more] SDM2012-75 ICD2012-43
MRIS, ITE-MMS 2011-10-14
Niigata Kashiwazaki energy hall, Niigata [Invited Talk] Nonvolatile Logic Systems Based on CMOS/Spintronics Hybrid Technology: An Overview
Satoshi Sugahara, Yusuke Shuto, Syuuichiro Yamamoto (Tokyo Insr. of Tech.) MR2011-18
 [more] MR2011-18
 Results 1 - 7 of 7  /   
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