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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2022-09-08
09:45
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
FPGA implementation of small area sum-of-products arithmetic unit for Posit and consideration of its introduction into AI chip ReNA
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-33
 [more] RECONF2022-33
pp.23-28
RECONF 2022-09-08
10:10
Aichi emCAMPUS STUDIO
(Primary: On-site, Secondary: Online)
Proposal and evaluation of Combined Posit MAC unit (CPMAC) for both DNN inference and training
Yuta Masuda, Yasuhiro Nakahara, Masato Kiyama, Masahiro Iida (Kumamoto Univ.) RECONF2022-34
Recently, there has been a lot of research on DNN hardware accelerators for the edge that use Posit as a number represen... [more] RECONF2022-34
pp.29-34
VLD, DC, RECONF, ICD, IPSJ-SLDM
(Joint) [detail]
2021-12-01
10:35
Online Online Basic evaluation of ReNA, a DNN accelerator using numerical representation posit
Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32
In Convolutional Neural Network (CNN) accelerators for edge, numerical precision of data should be reduced as much as po... [more] VLD2021-24 ICD2021-34 DC2021-30 RECONF2021-32
pp.43-48
RECONF 2021-06-08
16:10
Online Online Automatic generation of executable code for ReNA
Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) RECONF2021-6
We have been developing ReNA as a CNN accelerator for the edge, which is controlled by directly specifying control signa... [more] RECONF2021-6
pp.26-31
 Results 1 - 4 of 4  /   
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