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Committee Date Time Place Paper Title / Authors Abstract Paper #
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:25		 Kochi Kochi University of Technology (Kochi) Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32		 Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
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