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DC 2008-10-20
13:55		 Tokyo National Center of Sciences An implementation of a fault-tolerant 2D systolic array on an FPGA and its evaluation
Tadayoshi Horita (Polytechnic Univ.), Itsuo Takanami (Ichinoseki National College of Tech. in former times) DC2008-23		 A fault-tolerant self-reconfigurable 2D systolic array to calculate matrix multiplications is implemented on an FPGA.
... [more]		 DC2008-23
pp.7-12
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