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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CS, CAS | 2020-02-27 11:45 |
Kumamoto | Detecting Resistive-Open Defects of Power TSVs in 3D-ICs Koutaro Hachiya (Teikyo Heisei Univ.), Atsushi Kurokawa (Hirosaki Univ.)  CAS2019-104 CS2019-104 |
A method is proposed which detects resistive-open defects of power TSVs in PDNs by measuring resistance between power mi... [more] | CAS2019-104 CS2019-104 pp.37-41 |
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| SDM | 2016-01-22 14:35 |
Tokyo | Sanjo Conference Hall, The University of Tokyo | [Invited Talk]
Effect of Wafer Thinning on DRAM Characteristics for Bumpless Interconnects and WOW Applications Y. S. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto (Tokodai), A. Kawai (DISCO), T. Ohba (Tokodai) SDM2015-116 |
(To be available after the conference date) [more] | SDM2015-116 pp.33-37 |
| ICD, IE, VLD, IPSJ-SLDM [detail] | 2015-10-26 15:25 |
Miyagi | A Power-Efficient Memory Hierarchy Design for the 3D Integration Era Wataru Uno, Masayuki Sato, Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.) VLD2015-30 ICD2015-43 IE2015-65 |
3D-stacked memories are expected to play key roles to realize high-performance and low-power computing systems. This pap... [more] | VLD2015-30 ICD2015-43 IE2015-65 pp.19-24 |
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| SDM | 2014-02-28 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Impact of Back Grind Damage on Si Wafer Thinning for 3D Integration Yoriko Mizushima (Fujitsu Lab./Tokyo Inst. of Tech.), Youngsuk Kim (Tokyo Inst. of Tech./Disco), Tomoji Nakamura (Fujitsu Lab.), Ryuichi Sugie, Hideki Hashimoto (Toray Research Center), Akira Uedono (Univ. of Tsukuba), Takayuki Ohba (Tokyo Inst. of Tech.) SDM2013-167 |
Ultra-thin wafer is indispensable for bumpless 3D stacking. To know the thinning damage in detail, an atomic level defec... [more] | SDM2013-167 pp.13-18 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:20 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Three-Dimensional Accelerator Architecture for Image Recognition Shinya Ueno, Gauthier Lovic Eric, Koji Inoue, Kazuaki Murakami (Kyushu Univ.) SIP2011-63 ICD2011-66 IE2011-62 |
Image recognition used widely in several areas needs high-performance and low power processor. Accelerator is an effecti... [more] | SIP2011-63 ICD2011-66 IE2011-62 pp.7-12 |
| SDM | 2011-02-07 15:25 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Development of Low Temperature Bump-less TSV Process in 3D Stacking Technology Hideki Kitada, Nobuhide Maeda (The Univ. of Tokyo), Koji Fujimoto (Dai Nippon Printing), Yoriko Mizushima, Yoshihiro Nakata, Tomoji Nakamura (Fujitsu Laboratories Ltd.), Takayuki Ohba (The Univ. of Tokyo) SDM2010-224 |
Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vap... [more] | SDM2010-224 pp.49-53 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 11:05 |
Kanagawa | Hiyoshi Campus, Keio University | Implementation of 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication Shotaro Saito, Yasufumi Sugimori, Yoshinori Kohama, Tadahiro Kuroda, Yohei Hasegawa, Hideharu Amano (Keio Univ.) VLD2007-123 CPSY2007-66 RECONF2007-69 |
This paper describes the physical design and evaluation of 3-D dynamically reconfigurable processor MuCCRA-Cube which co... [more] | VLD2007-123 CPSY2007-66 RECONF2007-69 pp.31-36 |
| RECONF | 2007-05-17 15:10 |
Ishikawa | Kanazawa Bunka Hall | 3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication MuCCRA-Cube Shotaro Saito, Yohei Hasegawa, Yoshinori Kohama, Yasufumi Sugimori, Hideharu Amano (Keio Univ.) RECONF2007-5 |
In typical dynamically reconfiguarable devices, the overhead for programmable wires often forms critical paths by stretc... [more] | RECONF2007-5 pp.25-30 |
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