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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 9 of 9  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2021-08-18
Online Online [Invited Talk] A 12nm autonomous driving processor running 60.4 TOPS and 13.8 TOPS/W CNNs with task-separated ASIL D control
Katsushige Matsubara, Lieske Hanno (Renesas Electronics), Motoki Kimura (Renesas Electronics Europe), Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei (Renesas Electronics) SDM2021-39 ICD2021-10
Next-generation driver assistance systems and automated driving systems require both high performances to realize enormo... [more] SDM2021-39 ICD2021-10
(Joint) [detail]
Ehime Ehime Prefecture Gender Equality Center A Generation Method of Easily Testable Functional k Time Expansion Model for a Transition Fault Model Using Controller Augmentation and Partial Scan Designs
Yuta Ishiyama, Toshinori Hosokawa, Yuki Ikegaya (Nihon Univ.) VLD2019-43 DC2019-67
One of the challenges on VLSI testing is to reduce the area overhead and test application time of design-for-testability... [more] VLD2019-43 DC2019-67
DC 2019-02-27
Tokyo Kikai-Shinko-Kaikan Bldg. A Compaction Method for Test Sensitization State in Controllers
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.) DC2018-80
One of the challenges on VLSI testing is to reduce the area overhead of design-for-testability and to increase the fault... [more] DC2018-80
ICD, SDM, ITE-IST [detail] 2016-08-03
Osaka Central Electric Club [Invited Talk] A 16nm FinFET Heterogeneous Nona-Core SoC Supporting Functional Safety Standard ISO26262 ASIL B
Chikafumi Takahashi, Shinichi Shibahara, Kazuki Fukuoka, Jun Matsushima, Yuko Kitaji (Renesas System Design), Yasuhisa Shimazaki, Hirotaka Hara, Takahiro Irita (Renesas Electronics) SDM2016-64 ICD2016-32
This paper presents an SoC for the next generation of car infotainment, achieving high performance powered by nine heter... [more] SDM2016-64 ICD2016-32
DC 2016-06-20
Tokyo Kikai-Shinko-Kaikan Bldg. A Binding Method for Testability to Generate Easily Testable Functional Time Expansion Models
Mamoru Sato, Toshinori hosokawa, Tetsuya Masuda, Jun Nishimaki (Nihon Univ.), Hideo Fujiwara (Osaka Gakuin Univ.) DC2016-14
A test generation method for datapaths using easily testable functional time expansion models was proposed as efficient ... [more] DC2016-14
NLP 2015-05-19
Aomori Yu-sa Asamushi A Method for Determining Parameter Values of the Cochlea Reflectionless Transmission-Line Model
Takemori Orima, Yoshihiko Horio (Tokyo Denki Univ.), Tohru Kohda (Kyushu Univ.) NLP2015-35
Cochlea models are good candidates for a high-performance frequency analyzer. The passive transmission-line model propos... [more] NLP2015-35
DC 2014-12-19
Toyama   [Invited Talk] Trends in the international safety standard for motorcycles
Sei Takahashi (Nihon Univ.) DC2014-77
ISO 26262 (Road vehicles -- Functional safety) was published in November 2011. In this standard, hazardous events associ... [more] DC2014-77
DC 2013-06-21
Tokyo Kikai-Shinko-Kaikan Bldg. A Controller Augmentation Method to Generate Functional k-Time Expansion Models for Data Path Circuits
Yusuke Kodama, Jun Nishimaki, Tetsuya Masuda, Toshinori Hosokawa (Nihon Univ), Hideo Fujiwara (Osaka Gakuin Univ) DC2013-10
In recent years, various high-level test synthesis methods for LSIs have been proposed for the improvement in design pro... [more] DC2013-10
RECONF 2011-05-13
Hokkaido Hokkaido Univ. (Faculty of Eng., B3 Bldg.) A Homogeneous Routing Architecture for Efficient FPGA Design
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-19
In previous work, we have designed a prototype chip of island-style FPGA architecture. This architecture has very comple... [more] RECONF2011-19
 Results 1 - 9 of 9  /   
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