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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
EMM, IT 2023-05-12
Kyoto Rakuyu Kaikan (Kyoto Univ. Yoshida-South Campus)
(Primary: On-site, Secondary: Online)
Gradient flow decoding for LDPC codes
Tadashi Wadayama, Kensho Nakajima, Ayano Nakai-Kasai (NiTech) IT2023-8 EMM2023-8
The power consumption of the integrated circuit is becoming a significant burden, particularly for large-scale signal pr... [more] IT2023-8 EMM2023-8
HWS, VLD 2023-03-03
(Primary: On-site, Secondary: Online)
Track Assignment considering Routing Crossing Relations to Improve Feasibility in Bottleneck Channel Routing
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Molongo Mathieu, Makoto Minami, Katsuya Nishioka (Jedat) VLD2022-101 HWS2022-72
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2022-101 HWS2022-72
VLD, HWS [detail] 2022-03-07
Online Online Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Tech), Yukichi Todoroki, Makoto Minami (Jedat) VLD2021-77 HWS2021-54
Design automation that realizes analog integrated circuits to meet performance specifications in a small area is desired... [more] VLD2021-77 HWS2021-54
NLP 2021-12-18
Oita J:COM Horuto Hall OITA Experiment of time series signal classification task using 3D cyclic chaotic neural network reservoir
Takemori Orima, Yoshihiko Horio (Tohoku Univ.) NLP2021-65
The chaotic neural network reservoir composed of chaotic neurons can perform time-series signal processing with a smalle... [more] NLP2021-65
ICD 2018-04-19
Tokyo   [Invited Talk] VLSI implementation of chaotic Boltzmann machine for deep learning hardware
Takashi Morie, Masatoshi Yamaguchi, Ichiro Kawashima, Hakaru Tamukoh (Kyushu Inst. of Tech.) ICD2018-4
The Boltzmann machine (BM) model has been proposed as an optimization-problem solver as well as a learning machine using... [more] ICD2018-4
ICD, CPSY, CAS 2017-12-14
Okinawa Art Hotel Ishigakijima An Almost Digitally Synthesizable SAR-ADC
Kenshu Komatsu, Zule Xu, Takayuki Kawahara (TUS) CAS2017-95 ICD2017-83 CPSY2017-92
We are considering the stakelization of ADC, which is indispensable in integrated circuits, especially trying to realize... [more] CAS2017-95 ICD2017-83 CPSY2017-92
(Joint) [detail]
Kumamoto Kumamoto-Kenminkouryukan Parea Design of Weak-Signal-Readout-System for Terahertz-Video-Imaging
Toshiyuki Kikkawa, Makoto Ikeda (The Univ. of Tokyo) CPM2017-83 ICD2017-42 IE2017-68
In this paper, a weak-signal-readout-system for Terahertz-Video-Imaging is designed.
The system is integrated as 8$time... [more]
CPM2017-83 ICD2017-42 IE2017-68
MWP 2014-11-05
Miyagi RIEC, Tohoku Univ. [Invited Talk] Improvement of Disaster Resiliency and Access Technology of Optical Networks -- Accommodation of RoF Signals in the Optical Packet and Circuit Integrated Networks --
Masaki Shiraiwa, Sugang Xu, Yoshinari Awaji, Naoya Wada, Takaya Miyazawa, Hiroaki Harai, Atsushi Kanno, Toshiaki Kuri, Tetsuya Kawanishi (NICT) MWP2014-44
To increase the total capacity of radio access networks, the introduction of small-cell architectures will be indispensa... [more] MWP2014-44
SCE 2014-07-23
Tokyo Kikai-Shinko-Kaikan Bldg. Prototypes of Single-Chip Voltage Waveform Generators Based on SFQ Pulse-Frequency Modulation
Yoshinao Mizugaki, Keisuke Kuroiwa, Yusuke Sato, Yoshitaka Takahashi, Hiroshi Shimada (Univ. of Electro-Comm.), Masaaki Maezawa (AIST) SCE2014-31
We have been developing single-chip voltage waveform generators based on single-flux-quantum (SFQ) pulse-frequency modul... [more] SCE2014-31
ICD 2014-01-28
Kyoto Kyoto Univ. Tokeidai Kinenkan [Invited Talk] Analog mixed-signal circuit technique for micro/nano sensor devices
Ippei Akita (Toyohashi Tech) ICD2013-101
Precision analog frontend (AFE) circuits are desired in advanced arrayed sensor devices and such a circuit has to be opt... [more] ICD2013-101
MW 2013-03-08
Hiroshima Hiroshima Univ. [Special Invited Talk] Current Status and Future Prospect for Analog and RF CMOS Integrated Circuits
Akira Matsuzawa (Tokyo Inst. of Tech.) MW2012-185
Current status and future prospect for analog and RF CMOS integrated circuits will be discussed. The physical relationsh... [more] MW2012-185
CAS, CS, SIP 2012-03-09
Niigata The University of Niigata A construction of a floating-type scaling capacitor
Tatsuya Fujii, Fujihiko Matsumoto, Takeshi Ohbuchi, Tomomi Abe (NDA) CAS2011-141 SIP2011-161 CS2011-133
Impedance scaling technique is known as a method to reduce area of large capacitances for low frequency integrated filte... [more] CAS2011-141 SIP2011-161 CS2011-133
CAS 2012-01-20
Fukuoka Kyushu Univ. Phase Reduction Analysis on Noise-induced Synchronization among Nonlinear Oscillator Circuits
Kazuki Nakada (Kyusu Univ.), Keiji Miura (Tohoku Univ.), Tetsuya Asai (Hokkaido Univ.) CAS2011-101
We propose a design approach for optimization of noise-induced synchronization among analog sub-RF CMOS oscillator circu... [more] CAS2011-101
CAS 2012-01-20
Fukuoka Kyushu Univ. [Invited Talk] Balanced Three-Phase Analog Signal Processing and Circuits for Radio Communication
Takafumi Yamaji (Toshiba) CAS2011-103
Radio communication systems often use two analog signals as real and imaginary parts of a complex number, and the two si... [more] CAS2011-103
CAS, MSS, VLD, SIP 2010-06-21
Hokkaido Kitami Institute of Technology Layout-Aware Variation Modeling and Its Application to Opamp Design
Kouta Shinohara, Mihoko Hidaka, Qing Dong, Jing Li, Shigetoshi Nakatake (Univ. of Kitakyushu) CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7
As geometrical scaling of the transistor dimensions, such as feature
size and supply voltage, has dominated the semicon... [more]
CAS2010-7 VLD2010-17 SIP2010-28 CST2010-7
EMCJ, ITE-BCT 2010-03-12
Tokyo Kikai-Shinko-Kaikan Bldg. Design and Fabrication of On-chip Integrated Magnetic Field Probe using Low Noise Amplifier
Shiori Namba, Wataru Kodate, Masahiro Yamaguchi (Tohoku Univ.), Shoji Kawahito (Shizuoka Univ.), Noboru Ishihara (Tokyo Inst. of Tech.) EMCJ2009-132
An on-chip integrated magnetic field probe has been designed and fabricated using CMOS technology. This probe will be us... [more] EMCJ2009-132
SCE 2010-01-20
Tokyo Kikai-Shinkou-Kaikan Bldg. Operation of Variable SFQ Pulse Number Multiplier Designed for D/A Converter
Jun Saito, Takeyuki Tanaka, Masataka Moriya, Tadayuki Kobayashi, Yoshinao Mizugaki (UEC), Masaaki Maezawa (AIST) SCE2009-24
A Rapid Single Flux Quantum digital-to-analog converter (RSFQ-DAC) is a candidate for the next generation of ac voltage ... [more] SCE2009-24
ICD 2009-12-15
Shizuoka Shizuoka University (Hamamatsu) [Invited Talk] History and Technology Trends of Si RF Analog LSI Developments -- Emergence of New-Type Circuit Designers --
Tsuneo Tsukahara (Univ. of Aizu) ICD2009-96
The history of silicon RF analog circuits is described, focusing on the development of CMOS RF circuits. Moreover, the e... [more] ICD2009-96
NLP 2009-11-13
Kagoshima   A CMOS Frequency Comparator based on Jamming Avoidance Response of Eigenmannia -- A CMOS decoder circuit extracting frequency difference from amplitudes and phases of EODs --
Daichi Fujita, Tetsuya Asai, Yoshihito Amemiya (Hokkaido Univ.) NLP2009-111
In this paper, we implement a model of an electric fish, \textit{Eigenmannia}, that detects frequency differences betwee... [more] NLP2009-111
EMD 2009-03-06
Tokyo Kougakuin Univ. Simulation study of analog input buffer characteristics in CMOS integrated circuits
Yuuto Horiki, Keiko Fukuda (Tokyo Metropolitan Coll. of Ind Tech.) EMD2008-144
Complementary-type analog input buffer is proposed for low-voltage operation in CMOS integrated circuits. It consists o... [more] EMD2008-144
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