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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-01 14:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
A Study on Interface Circuits for Burst Transfers from Synchronous to Asynchronous Circuits Shogo Semba, Hiroshi Saito (UoA)  VLD2022-78 HWS2022-49 |
In this paper, we propose interface circuits for burst transfers from synchronous to asynchronous circuits. The proposed... [more] | VLD2022-78 HWS2022-49 pp.31-36 |
| HWS, VLD | 2023-03-02 09:55 |
Okinawa | (Primary: On-site, Secondary: Online) |
Implementation of power-outage tolerant VLSI system using asynchronous circuits Masashi Imai (Hirosaki Univ.) VLD2022-86 HWS2022-57 |
Re-initialization free systems which contain nonvolatile memory have been proposed in order to cope with power-outage. H... [more] | VLD2022-86 HWS2022-57 pp.79-84 |
| VLD, HWS [detail] | 2022-03-08 09:30 |
Online | Online | A Study on Interface Circuits Using Click Element Between Synchronous-asynchronous Domains Shogo Semba, Hiroshi Saito (UoA) VLD2021-91 HWS2021-68 |
In this paper, we propose interface circuits using Click Element between synchronous and asynchronous domains. The propo... [more] | VLD2021-91 HWS2021-68 pp.81-86 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 15:35 |
Online | Online | Evaluation of Side-channel Leakage on High-speed Asynchronous Successive Approximation Register AD Converters Ryozo Takahashi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) SDM2021-43 ICD2021-14 |
This paper presents an evaluation of security level on high-speed asynchronous successive approximation register (SAR) a... [more] | SDM2021-43 ICD2021-14 pp.68-71 |
| HWS, VLD [detail] | 2020-03-04 13:25 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Study of Dynamic Power Optimization by Latch Insertion for Asynchronous RTL Models Shogo Semba, Hiroshi Saito (UoA) VLD2019-100 HWS2019-73 |
In this paper, we propose a dynamic power optimization method by latch insertion for asynchronous RTL models. In data-pa... [more] | VLD2019-100 HWS2019-73 pp.37-42 |
| HWS, ICD [detail] | 2019-11-01 16:00 |
Osaka | DNP Namba SS Bld. | A Study of Hardware Trojan Detection Method using Deep Learning in Asynchronous Circuits Hikaru Inafune, Masashi Imai (Hirosaki Univ.) HWS2019-63 ICD2019-24 |
There are typically two timing methods in VLSI designs known as synchronous circuits which use a global clock and async... [more] |
HWS2019-63 ICD2019-24 pp.35-40 |
| MSS, CAS, SIP, VLD | 2019-07-31 16:45 |
Iwate | Iwate Univ. | Speedup of the Asynchronous Serial Multiplier by Concealing the Idle Phase for Digital Hearing Aids Masahiro Nagata (Okayama Prefectural Univ.), Masafumi Kondo, Isao Kayono (Kawasaki Univ. of Medical Welfare), Tomoyuki Yokogawa, Kazutami Arimoto, Yoichiro Sato (Okayama Prefectural Univ.) CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 |
Recently, digital hearing aids with DSP have spread through, but their battery life has remained for only a few days. Fo... [more] | CAS2019-22 VLD2019-28 SIP2019-38 MSS2019-22 pp.99-104 |
| HWS, VLD | 2019-03-01 10:25 |
Okinawa | Okinawa Ken Seinen Kaikan | A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs Tatsuki Otake, Hiroshi Saito (UoA) VLD2018-123 HWS2018-86 |
In this work, we study placement constraints for asynchronous circuits with bundled-data implemen-tation aimed for Field... [more] | VLD2018-123 HWS2018-86 pp.181-186 |
| VLD, HWS (Joint) |
2018-03-01 13:25 |
Okinawa | Okinawa Seinen Kaikan | A Study on Energy Optimization for Asynchronous RTL Models with Bundled-data Implementation Shogo Semba, Hiroshi Saito (UoA) VLD2017-111 |
In this work, we study two energy optimization methods for asynchronous RTL models with bundled-data implementation. The... [more] | VLD2017-111 pp.133-138 |
| VLD | 2017-03-01 16:20 |
Okinawa | Okinawa Seinen Kaikan | Implementation of a Transformation tool from Synchronous RTL Models to Asynchronous RTL Models Shogo Senba, Hiroshi Saito (UoA) VLD2016-107 |
This paper proposes a transformation tool that generates an asynchronous Register Transfer Level (RTL) model with bundle... [more] | VLD2016-107 pp.31-36 |
| VLD, CAS, MSS, SIP | 2016-06-17 15:50 |
Aomori | Hirosaki Shiritsu Kanko-kan | A Study on Fault Tolerant Features of Asynchronous Circuits using Voted-enable Latches Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33 |
A bit flip caused by voltage fluctuation, soft errors, and hardware Trojans becomes one of serious issues in the modern ... [more] | CAS2016-33 VLD2016-39 SIP2016-67 MSS2016-33 pp.179-184 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 13:45 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Evaluation of Low-Voltage Characteristics of QDI model based Asynchronous VLSI Ryuhei Tachika, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-67 DC2015-63 |
In synchronous circuits, it is needed to distribute an identical clock signal to the whole chip with a constant frequenc... [more] | VLD2015-67 DC2015-63 pp.189-194 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 14:10 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan | Implementation and Evaluation of Peak Current Reduction Bandpass Filter using Asynchronous Circuits Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) VLD2015-68 DC2015-64 |
In synchronous circuits, peak currents flow at a constant frequency since a global clock signal which is a timing signal... [more] | VLD2015-68 DC2015-64 pp.195-200 |
| DC | 2015-06-16 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Study on Function Test of Latch-based Asynchronous Pipeline Circuits Daiki Toyoshima, Kyohei Terayama, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ.) DC2015-19 |
Asynchronous MOUSETRAP pipeline circuit is a simple and fast circuit thanks to the 2-phase handshaking protocol which ha... [more] | DC2015-19 pp.19-24 |
| SDM, EID | 2014-12-12 14:00 |
Kyoto | Kyoto University | Characterization of Synchronous and Asynchronous Circuits using poly-Si TFTs Yosuke Nagase (Ryukoku Univ.), Tokiyoshi Matsuda, Mutsumi Kimura (Osaka Univ.), Taketoshi Matsumoto, Hikaru Kobayashi (Ryukoku Univ.) EID2014-25 SDM2014-120 |
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the ou... [more] | EID2014-25 SDM2014-120 pp.61-65 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations Shunya Hosaka, Hiroshi Saito (Univ. Aizu) VLD2014-104 DC2014-58 |
In this paper, we study a dynamic power optimization method for asynchronous circuits with bundled-data implementation u... [more] | VLD2014-104 DC2014-58 pp.215-220 |
| VLD, IPSJ-SLDM | 2014-05-29 11:05 |
Fukuoka | Kitakyushu International Conference Center | Proposal of a Synthesis Flow for Asynchronous Circuits with Bundled-Data Implementation from a SystemC Model Taichi Komine, Hiroshi Saito (Univ. of Aizu) VLD2014-5 |
This paper proposes a synthesis flow for asynchronous circuits with bundled-data implementation from a SystemC model to ... [more] | VLD2014-5 pp.21-26 |
| CPSY, DC | 2014-04-25 14:00 |
Tokyo | Construction of Design Environment for Asynchronous Circuits using DDL Cell Library Masashi Imai, Hiromasa Igarashi, Sanshiro Kudo (Hirosaki Univ.) CPSY2014-2 DC2014-2 |
As the VLSI fabrication technology advances, delay variations due to random process variations, crosstalk, and aging eff... [more] | CPSY2014-2 DC2014-2 pp.3-8 |
|
| DC | 2014-02-10 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A DFT Method to Achieve 100% Fault Coverage for QDI Asynchronous Circuit Sanae Mizutani, Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT) DC2013-81 |
With the advances of semiconductor process technologies, synchronous circuits have serious problems of thr clock. Asynch... [more] | DC2013-81 pp.13-18 |
| IPSJ-SLDM, CPSY, RECONF, VLD [detail] | 2014-01-28 11:40 |
Kanagawa | Hiyoshi Campus, Keio University | Reduction Method of Asynchronous Circuits with Maximum Delay Loops using SDI Delay Assumption Tomoya Tasaki, Hiroto Kagotani, Yuji Sugiyama (Okayama Univ.) VLD2013-109 CPSY2013-80 RECONF2013-63 |
As one of the design methods of asynchronous pipeline circuits, a synthesis algorithm using dependency graphs has been p... [more] | VLD2013-109 CPSY2013-80 RECONF2013-63 pp.43-48 |
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