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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 12 of 12  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2020-02-26
16:35		 Tokyo   Soft Error Tolerance of Power-Supply-Noise Hardened Latches
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2019-97		 In recent years, with the scaling down and low-power operation of VLSI circuits, reliability degradation due to soft err... [more] DC2019-97
pp.67-72
DC 2019-02-27
15:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise
Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2018-82		 With the scaling down and low-power operation of VLSI circuits, influence on circuit behavior by power supply noise such... [more] DC2018-82
pp.67-72
DC 2018-02-20
16:35		 Tokyo Kikai-Shinko-Kaikan Bldg. Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures
Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-88		 With the scaling down and low power operation of VLSI circuits, effects on circuit behavior by power supply noise such a... [more] DC2017-88
pp.67-72
DC 2016-02-17
16:05		 Tokyo Kikai-Shinko-Kaikan Bldg. Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96		 According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the o... [more] DC2015-96
pp.61-66
DC 2015-06-16
14:10		 Tokyo Kikai-Shinko-Kaikan Bldg. A test data reduction method based on scan slice on BAST
Makoto Nishikiori, Hiroshi Yamazaki, Toshinori Hosokawa, Masayuki Arai (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2015-16		 BAST is one of techniques to reduce the amount of test data while maintaining high test quality by combining built-in se... [more] DC2015-16
pp.1-6
DC 2014-02-10
15:10		 Tokyo Kikai-Shinko-Kaikan Bldg. A reduction method of shift data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ) DC2013-87		 BAST is one of techniques to reduce the amount of test data while maintaining the high test quality using built-in self ... [more] DC2013-87
pp.49-54
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2013-11-28
14:10		 Kagoshima   An inverter block construction method to reduce test data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute) VLD2013-85 DC2013-51		 BAST is one of technique to reduce the amount of test data while maintaining the high test quality using built-in self t... [more] VLD2013-85 DC2013-51
pp.171-176
IT, ISEC, WBS 2013-03-07
14:30		 Osaka Kwansei Gakuin Univ., Osaka-Umeda Campus Performance Evaluation of a Combination of Sum-Product and Two-bit Bit Flipping Decoding Algorithms
Koh Matsushita, Hiroshi Kamabe (Gifu Univ.) IT2012-72 ISEC2012-90 WBS2012-58		 A Bit-Flipping algorith which uses only two bits for each node has been proposed. The bit error probability of the metho... [more] IT2012-72 ISEC2012-90 WBS2012-58
pp.65-70
NS, RCS
(Joint)		 2011-12-15
09:10		 Yamaguchi Yamaguchi University Investigation of Dual Threshold Scaling Factors for Bit Flip Decoding
Julian Webber, Toshihiko Nishimura, Takeo Ohgane, Yasutaka Ogawa (Hokkaido Univ.) RCS2011-232		 Very low error rates can be obtained using low-density parity-check (LDPC) codes and their use is now common in new comm... [more] RCS2011-232
pp.1-6
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]		 2011-11-29
09:50		 Miyazaki NewWelCity Miyazaki A Scan Chain Construction Method to Reduce Test Data Volume on BAST
Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) VLD2011-73 DC2011-49		 BAST is one of techniques which are combined ATPG and BIST to reduce the amount of test data while maintaining the high ... [more] VLD2011-73 DC2011-49
pp.127-132
DC 2009-02-16
15:20		 Tokyo   A Method to Increase the Number of Don't care based on Easy- To-Detected Faults -- Application for BAST Architecture --
LingLing Wan (Graduate Schoo of Nihon Univ.), Motohiro Wakazono (Graduate School of Nihon Univ.), Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) DC2008-76		 The BIST Aided Scan Test (BAST) is a technique that combines the
automatic test pattern generator (ATPG) and the Built-... [more]		 DC2008-76
pp.49-54
CS, CQ
(Joint)		 2008-04-24
14:55		 Aomori Hirosaki University A Study on Rate Estimation Scheme for Weighted Bit-Flipping Decoding of Rate Compatible LDPC Codes
Kenji Kita, Tetsuo Tsujioka (Osaka City Univ.) CS2008-1		 This paper considers a rate estimation scheme for Rate Compatible LDPC (RC-LDPC) codes. The authors have investigated so... [more] CS2008-1
pp.1-6
 Results 1 - 12 of 12  /   
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