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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, RCS (Joint) |
2023-12-15 10:15 |
Fukuoka | Kyushu Institute of Technology Tobata campus, and Online (Fukuoka, Online) (Primary: On-site, Secondary: Online) |
[Encouragement Talk]
Uncore frequency scaling method based on detecting server throughput saturation Katsumi Fujita, Hirofumi Noguchi, Masashi Kaneko (NTT)  NS2023-142 |
Data centers account for 1% of total global power consumption. Reducing a data center's energy costs is a significant is... [more] | NS2023-142 pp.97-102 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2021-03-26 14:20 |
Online | Online (Online) | IPC control mechanism for highly efficient RT-DVFS Atsushi Santo, Nobuyuki Yamasaki (Keio Univ.) CPSY2020-65 DC2020-95 |
Embedded real-time systems requires power consumption while satisfying real-time performance. RT-DVFS and real-time sch... [more] | CPSY2020-65 DC2020-95 pp.91-96 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-17 15:50 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) (Kagoshima) | Real-Time Voltage and Frequency Scaling Scheme with IPC Controlling for SMT Processor Hiromi Suzuki, Yousuke Ide, Yuta Tsukahara, Nobuyuki Yamasaki (Keio Univ) CPSY2018-106 DC2018-88 |
In the field of Real-Time embedded systems, both of high-performance and low-power consumption are required. In this pap... [more] | CPSY2018-106 DC2018-88 pp.161-166 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2015-12-03 10:50 |
Nagasaki | Nagasaki Kinro Fukushi Kaikan (Nagasaki) | Cache Energy Reduction by Switching between L1 High Power and Low Power Cache under DVFS Environment Kaoru Saito, Ryotaro Kobayashi (Toyohashi Univ of Tech), Hajime Shimada (Nagoya Univ.) CPSY2015-72 |
Current CPU utilizes cache memory for decreasing an access speed gap between CPU and main memory. But the cache occupie... [more] |
CPSY2015-72 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-27 11:10 |
Kagoshima | (Kagoshima) | A Quantizer Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.) CPM2013-113 ICD2013-90 |
To make full use of the advantages of dynamic voltage and frequency scaling (DVFS) technique, a quantization decoder (Q... [more] | CPM2013-113 ICD2013-90 pp.31-36 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] | 2013-03-14 10:00 |
Nagasaki | (Nagasaki) | A Temperature-Aware DVFS Control on Imprecise Computation Model Keigo Mizotani, Rikuhei Ueda, Masayoshi Takasu, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2012-88 DC2012-94 |
As microprocessor grows in density, management of processor temperature is becoming an important issue. Temperature-Awar... [more] | CPSY2012-88 DC2012-94 pp.217-222 |
| IE, SIP, ICD, VLD, IPSJ-SLDM [detail] | 2012-10-19 13:50 |
Iwate | Hotel Ruiz (Iwate) | A Low Power CMOS Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling (DVFS) and Adaptively Assigned Breaking-off Condition (A2BC) Motion Estimation Algorithm Tadayoshi Enomoto, Nobuaki Kobayashi (Chuo Univ) VLD2012-53 SIP2012-75 ICD2012-70 IE2012-77 |
A motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) technique to ... [more] | VLD2012-53 SIP2012-75 ICD2012-70 IE2012-77 pp.71-76 |
| ICD, SDM | 2012-08-03 13:10 |
Hokkaido | Sapporo Center for Gender Equality, Sapporo, Hokkaido (Hokkaido) | A Fast-Transient-Response Digital Low-Dropout Regulator Comprising Thin-Oxide MOS Transistors in 40-nm CMOS process Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita (Renesas Electronics), Koichiro Ishibashi (Univ. of Electro-Comm.), Kazumasa Yanagisawa (Renesas Electronics) SDM2012-82 ICD2012-50 |
A digital low-dropout (LDO) regulator comprising only thin-oxide MOS transistors was developed. The input voltage to the... [more] | SDM2012-82 ICD2012-50 pp.105-110 |
| VLD | 2012-03-07 13:20 |
Oita | B-con Plaza (Oita) | Power reduction of memory circuit and DVFS technique in Dynamic Reconfigurable Processor Yuki Hayakawa, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2011-138 |
This paper describes a DVFS technique to reduce energy dissipation of Dynamically Reconfigurable Processors(DRP). DRP’s ... [more] | VLD2011-138 pp.109-114 |
| PRMU, DE | 2011-06-06 11:00 |
Kanagawa | (Kanagawa) | An Experimental Study on Power Saving of Online Transaction Processing using Dynamic Voltage and Frequency Scaling in a SSD-equipped Environment Yuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa (The Univ. of Tokyo) DE2011-3 PRMU2011-34 |
Power consumption of datacenters has been increasing, and today its power saving is highly demanded. For power saving in... [more] | DE2011-3 PRMU2011-34 pp.13-18 |
| ICD, IPSJ-ARC | 2011-01-20 10:00 |
Kanagawa | Keio University (Hiyoshi Campus) (Kanagawa) | 3D-Packaging Method for Microminiature SiP using Hybrid FPC. Kikuo Wada, Ryouji Ohsu (NECAT), Shigekazu Hino (HINO Jisso Design), Nobuyuki Yamasaki (Keio University) |
(To be available after the conference date) [more] | ICD2010-129 pp.1-6 |
| DE | 2010-12-06 17:45 |
Tokyo | AIST Tokyo Akihabara Site (Tokyo) | An Experimental Study on Application-aware Power Saving Method for Online Transaction Processing using Dynamic Voltage and Frequency Scaling Yuto Hayamizu, Kazuo Goda, Miyuki Nakano, Masaru Kitsuregawa (Univ. of Tokyo) DE2010-37 |
Power consumption of servers in data centers has been growing rapidly recent years. Among these servers, power saving of... [more] | DE2010-37 pp.67-72 |
| ICD, SDM | 2010-08-26 13:50 |
Hokkaido | Sapporo Center for Gender Equality (Hokkaido) | Design Constraint of Fine Grain Supply Voltage Control LSI
-- In the case of DVFS Technique -- Atsuki Inoue (Fujitsu Lab. Ltd.) SDM2010-133 ICD2010-48 |
Supply voltage control technique for realizing low power LSI is utilized not only for general purpose processors but als... [more] | SDM2010-133 ICD2010-48 pp.51-54 |
| DE | 2010-08-04 15:00 |
Tokyo | Aoyama Gakuin University (Tokyo) | An Experimental Study on Energy Saving for Dynamic Voltage and Frequency Scaling in Online Transaction Processing Yuto Hayamizu, Kazuo Goda, Masaru Kitsuregawa (Univ. of Tokyo) DE2010-21 |
As IT systems play more important roles in our society, their complexity and the amount of processed data is growing. Th... [more] | DE2010-21 pp.41-46 |
| VLD, IPSJ-SLDM | 2010-05-20 13:05 |
Fukuoka | Kitakyushu International Conference Center (Fukuoka) | A Wide-Range Clock Synchronizer with Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS Control Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu (Hitachi), Yoshihiko Yasu, Koichiro Ishibashi (Renesas) VLD2010-7 |
A ``wide-range voltage-and-frequency clock synchronizer'' for maintaining synchronization during voltage-scaling transit... [more] | VLD2010-7 pp.67-72 |
| ICD | 2010-04-22 10:50 |
Kanagawa | Shonan Institute of Tech. (Kanagawa) | A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Yasunobu Nakase, Hirofumi Shinohara (Renesas Electronics) ICD2010-3 |
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. ... [more] | ICD2010-3 pp.13-16 |
| SIP, CAS, CS | 2010-03-02 13:45 |
Okinawa | Hotel Breeze Bay Marina, Miyakojima (Okinawa) | [Poster Presentation]
Low Power Processor Architecture based on a Dynamic Reconfigurable Scheme in Pipeline Stages Masashi Ohki, Nobuhiko Sugino (Tokyo Inst. of Tech.) CAS2009-120 SIP2009-165 CS2009-115 |
A processor architecture which can execute instructions in dynamic reconfigurable pipeline manner is proposed. By help o... [more] | CAS2009-120 SIP2009-165 CS2009-115 pp.237-238 |
| VLD | 2009-03-11 11:20 |
Okinawa | (Okinawa) | Execution Trace Mining for Intratask DVFS in Embedded Systems Tomohiro Tatematsu, Tetsuo Yokoyama, Takehiko Kikuchi, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) VLD2008-128 |
We propose execution trace mining for intratask DVFS (dynamic voltage and frequency scaling) in embedded systems to effe... [more] | VLD2008-128 pp.11-16 |
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