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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ)  VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| RECONF | 2017-09-25 13:55 |
Tokyo | DWANGO Co., Ltd. | A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) RECONF2017-25 |
The authors consider applying FPGA Dynamic Partial Reconfiguration (DPR) technique to carrier network equipment built wi... [more] | RECONF2017-25 pp.19-24 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-28 11:05 |
Kagoshima | [Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.) VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 |
Owing to wide spread of VLSI systems, a failure of the VLSIs may lead critical issue in our daily life. Especially in so... [more] | VLD2013-87 CPM2013-122 ICD2013-99 CPSY2013-63 DC2013-53 RECONF2013-51 p.183(VLD), p.81(CPM), p.81(ICD), p.27(CPSY), p.183(DC), p.69(RECONF) |
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| RECONF | 2013-09-19 14:50 |
Ishikawa | Japan Advanced Institute of Science and Technology | Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36 |
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] | RECONF2013-36 pp.97-102 |
| CPSY, VLD, RECONF, IPSJ-SLDM [detail] | 2013-01-17 13:25 |
Kanagawa | A Channel-based Communication/Synchronization Model for SW-HW Multitasking on Dynamically Partially Reconfigurable FPGAs Krzysztof Jozwik, Shinya Honda, Masato Edahiro (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) VLD2012-130 CPSY2012-79 RECONF2012-84 |
Dynamically Partially Reconfigurable (DPR) FPGAs allow for implementation of a concept of SW-HW multitasking where flow ... [more] | VLD2012-130 CPSY2012-79 RECONF2012-84 pp.135-140 |
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| RECONF | 2012-09-18 16:30 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-34 |
Dynamic and partial reconfiguration (DRP) on SRAM-based FPGAs has received increasing attention, since Xilinx Inc. start... [more] | RECONF2012-34 pp.61-66 |
| RECONF | 2012-09-19 09:00 |
Shiga | Epock Ritsumei 21, Ritsumeikan Univ. | Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-36 |
Some of recent FPGAs have the functionality of dynamic partial reconfiguration. By using this functionality, it is expec... [more] | RECONF2012-36 pp.73-78 |
| DC, CPSY (Joint) |
2012-08-03 09:30 |
Tottori | Torigin Bunka Kaikan | A development scheduling simulater for reconfiguable system Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19 |
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] | CPSY2012-19 pp.61-66 |
| ICD, IE, SIP, IPSJ-SLDM [detail] | 2011-10-24 14:45 |
Miyagi | Ｉｃｈｉｎｏｂｏ(Sendai) | Architecture of a Dynamically Reconfigurable VLSI Processor Based on Register-Transfer-Level Packet Transfer Yoshichika Fujioka (Hachinohe Inst. of Tech.), Sho Takizawa, Michitaka Kameyama (Tohoku Univ.) SIP2011-64 ICD2011-67 IE2011-63 |
Register-transfer-level packet routing scheme is proposed for intra-chip data transfer to make the size of configuration... [more] | SIP2011-64 ICD2011-67 IE2011-63 pp.13-18 |
| RECONF | 2011-09-26 15:30 |
Aichi | Nagoya Univ. | Preemptive Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs - Hardware and Reconfiguration Layers Krzysztof Jozwik, Shinya Honda (Nagoya Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroaki Takada (Nagoya Univ.) RECONF2011-29 |
Preemption techniques for HW (hardware) tasks have been studied in order to improve their responsiveness and to allow ... [more] |
RECONF2011-29 pp.43-48 |
| RECONF | 2011-09-27 09:50 |
Aichi | Nagoya Univ. | A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.) RECONF2011-34 |
In this study we implement a mechanism that makes it possible to execute dynamic and partial reconfigurationfrom remote ... [more] | RECONF2011-34 pp.69-74 |
| RECONF | 2011-05-12 13:30 |
Hokkaido | Hokkaido Univ. (Faculty of Eng., B3 Bldg.) | Context Synchronization Method for Reliable Softcore Processor System Makoto Fujino, Noritaka Kai, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-5 |
SRAM-based FPGAs are vulnerable to a SEU, which is induced by radiation effect. The SEU's effects on configuration mem... [more] |
RECONF2011-5 pp.25-30 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:20 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) VLD2010-102 CPSY2010-57 RECONF2010-71 |
Recently, the threat of side channel attack to the hardware encryption circuits is increasing. In order to cope with it... [more] |
VLD2010-102 CPSY2010-57 RECONF2010-71 pp.127-132 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] | VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 14:30 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77 |
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] | VLD2010-108 CPSY2010-63 RECONF2010-77 pp.163-168 |
| RECONF | 2010-09-16 11:00 |
Shizuoka | Shizuoka University (Faculty of Eng., Hall 2) | Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2010-18 |
In this paper, we develop an on-chip pattern recognition system. The feature of this system is that two Microblaze core... [more] |
RECONF2010-18 pp.1-6 |
| IPSJ-SLDM, VLD, CPSY, RECONF [detail] | 2010-01-27 10:25 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Effective Hardware Task Context Switching in Virtex-4 FPGAs Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada (Nagoya Univ.) VLD2009-87 CPSY2009-69 RECONF2009-72 |
A unique aspect of flexibility provided by some of the FPGAs such as Xilinx Virtex-4 family is the capability of dynamic... [more] | VLD2009-87 CPSY2009-69 RECONF2009-72 pp.113-118 |
| RECONF | 2009-05-15 12:40 |
Fukui | * Hiroyuki Kawai, Yoshiki Yamaguchi, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2009-13 |
In this paper, we extend DDI (Direct Data Implementation), that is pattern data are directly transformed into logic circ... [more] | RECONF2009-13 pp.73-78 |
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| VLD, CPSY, RECONF, IPSJ-SLDM | 2009-01-29 08:40 |
Kanagawa | Implementation of Dynamically Reconfigurable Processor MuCCRA-3 and Methods for Reconfiguration Overhead Reduction Toru Sano, Hideharu Amano (Keio Univ) VLD2008-91 CPSY2008-53 RECONF2008-55 |
We have developed and evaluated MuCCRA-1 and 2 in order to analyze architectural trade-off in dynamically reconfigurab... [more] |
VLD2008-91 CPSY2008-53 RECONF2008-55 pp.1-6 |
|
| CPSY | 2008-12-18 16:10 |
Kyoto | KYOTO Research Park | An Architecture of Dynamically Reconfigurable Systolic Array and FPGA Implementation Toshiyuki Ishimura, Yuhki Hayakawa, Akinori Kanasugi (Tokyo Denki Univ.) CPSY2008-52 |
The dynamically reconfigurable processors which have high-speed performance of ASIC, flexibility of FPGA and high area e... [more] | CPSY2008-52 pp.55-60 |
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