IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 4 of 4  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, HWS [detail] 2022-03-08
09:55
Online Online Wafer-Level Characteristic Variation Modeling with Considering Discontinuous Effect Caused by Manufacturing Equipment
Takuma Nagao (National Institute of Technology (KOSEN)), Michihiro Shintani (Nara Institute of Science and Technology), Ken'ichi Yamaguchi, Hiroshi Iwata (National Institute of Technology (KOSEN)), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (SCK), Michiko Inoue (Nara Institute of Science and Technology) VLD2021-92 HWS2021-69
Statistical methods for predicting the performance of large-scale integrated circuits (LSIs) manufactured on a wafer are... [more] VLD2021-92 HWS2021-69
pp.87-92
IN, CCS
(Joint)
2021-08-05
14:25
Online Online Digital Implement of 3-layered Neural Networks with Stochastic Activation, Shunting Inhibition, and a Dual-rail Backpropagation
Yoshiaki Sasaki, Seiya Muramatsu, Kohei Nishida, Megumi Akai-Kasaya, Tetsuya Asai (Hokkaido Univ.) CCS2021-16
Stochastic computing (SC) is an arithmetic technique that enables various operations to be performed with a small number... [more] CCS2021-16
pp.7-13
AP 2019-10-18
09:55
Osaka Osaka Univ. 28 GHz Side-Edge Loop Antenna with End-Fire Radiation Polarized Vertically to Substrate
Masayuki Nakajima (Antenna Giken) AP2019-98
Mm wave and quasi-mm wave high-speed wireless communication systems are being developed widely by leveraging silicon int... [more] AP2019-98
pp.95-100
SCE 2007-10-17
14:15
Tokyo Kikai-Shinko-Kaikan Bldg. Optimization in ramp fabrication process for high-Tc ramp-edge Josephson junction
Seiji Adachi, Kaku Igarashi, Kiyokazu Higuchi, Hironori Wakana (SRL), Nobuyuki Iwata, Hiroshi Yamamoto (Nihon Univ.), Keiichi Tanabe (SRL)
For fabrication of integrated circuits including high-Tc ramp-edge Josephson junctions, the establishment of preparation... [more] SCE2007-21
pp.17-21
 Results 1 - 4 of 4  /   
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan