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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| ISEC | 2019-05-17 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Talk]
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology (from DSD 2018) Jean-Luc Danger (Telecom ParisTech), Risa Yashiro (UEC), Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet (Telecom ParisTech), Kazuo Sakiyama (UEC), Noriyuki Miura, Makoto Nagata (Kobe University), Sylvain Guilley (Secure-IC)  ISEC2019-3 |
In this talk, we introduce the paper “Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology” by Je... [more] | ISEC2019-3 p.5 |
| QIT (2nd) |
2018-11-26 13:30 |
Tokyo | The University of Tokyo | [Poster Presentation]
Proposal of scalable silicon qubits with stacked structure for realizing multiple qubits Yuki Ito, Masaharu Kobayashi, Toshiro Hiramoto (IIS) |
We have proposed multiple silicon qubits with stacked structure. The qubits and single electron transistors (SETs) for r... [more] | |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-29 09:00 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Measurement of Vth Variation due to STI Stress and Inverse Narrow Channel Effect at Ultra-Low Voltage in a Variability-Suppressed Process Yasuhiro Ogasahara, Hanpei Koike (AIST) CPM2016-76 ICD2016-37 IE2016-71 |
This paper demonstrates notable impact of Vth shift due to STI-induced dopant redistribution on ultra-low voltage design... [more] | CPM2016-76 ICD2016-37 IE2016-71 pp.1-6 |
| ICD, SDM, ITE-IST [detail] | 2016-08-02 09:00 |
Osaka | Central Electric Club | [Invited Talk]
Soft Error Immunity of Ultra-Low Voltage SRAM Masanori Hashimoto (Osaka Univ.) SDM2016-54 ICD2016-22 |
This paper discusses soft error immunity of near-threshold/subthreshold SRAM. In terrestrial environment, high-energy ne... [more] | SDM2016-54 ICD2016-22 pp.53-58 |
| ICD | 2016-04-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | [Invited Lecture]
A 298-fJ/writecycle 650-fJ/readcycle 8T Three-Port SRAM in 28-nm FD-SOI Process Technology for Image Processor Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi, Shusuke Yoshimoto, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2016-3 |
This paper presents a low-power and low-voltage 64-kb 8T three-port image memory using a 28-nm FD-SOI process technology... [more] | ICD2016-3 pp.13-16 |
| ICD, SDM | 2014-08-05 14:55 |
Hokkaido | Hokkaido Univ., Multimedia Education Bldg. | Initial Frequency Degradation on Ring Oscillators in 65-nm SOTB Process Caused by Plasma-Induced Damage Azusa Oshima, Ryo Kishida, Michitarou Yabuuchi, Kazutoshi Kobayashi (KIT) SDM2014-79 ICD2014-48 |
Reliability issues, such as plasma-induced damage (PID) and Bias Temperature Instability (BTI), become dominant on inte... [more] |
SDM2014-79 ICD2014-48 pp.93-98 |
| ICD | 2014-01-28 15:00 |
Kyoto | Kyoto Univ. Tokeidai Kinenkan | [Poster Presentation]
Low-Power 28nm FD-SOI SRAM for Image Processor Yuta Kawamoto, Shusuke Yoshimoto, Tomoki Nakagawa, Yuki Kitahara, Haruki Mori, Kenta Takagi, Shintaro Izumi (Kobe Univ.), Koji Nii (Renesas Electronics), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2013-116 |
In recent years, image recognition has been applied to various fields such as an automatic driving system. SRAM (Static ... [more] | ICD2013-116 p.41 |
| ICD | 2011-12-16 14:25 |
Osaka | 0.42-V 576-kb 0.15-um FD-SOI SRAM with 7T/14T Bit Cells and Substrate Bias Control Circuits for Intra-Die and Inter-Die Variability Compensation Shusuke Yoshimoto, Kosuke Yamaguchi, Shunsuke Okumura, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ.) ICD2011-133 |
We propose 7T/14T FD-SOI SRAM with a substrate bias control mechanism. The 14T configuration suppresses intra-die variat... [more] | ICD2011-133 pp.155-160 |
|
| SDM, ICD | 2011-08-26 10:25 |
Toyama | Toyama kenminkaikan | [Invited Talk]
Status and Prospect of Ultra Low Power Logic Devices Jiro Ida (KIT) SDM2011-86 ICD2011-54 |
Ultra Low Power Application of Sensor network, or, implanted medical devices where battery less, ultimately, is needed, ... [more] | SDM2011-86 ICD2011-54 pp.79-83 |
| SANE | 2010-10-28 16:00 |
Overseas | Ramada Hotel, Jeju-do, Korea | [Invited Talk]
Cryogenic readout electronics for space borne far-infrared image sensors Hirohisa Nagata, Takehiko Wada, Hirokazu Ikeda (JAXA), Yasuo Arai (KEK), Morifumi Ohno (AIST) SANE2010-108 |
We have been developing low power cryogenic readout electronics for space borne large format far-infrared image sensors.... [more] | SANE2010-108 pp.229-234 |
| ICD | 2008-12-12 16:10 |
Tokyo | Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan | An Inter-Die Variability Compensation Scheme for 0.42-V 486-kb FD-SOI SRAM using Substrate Control Kosuke Yamaguchi, Hidehiro Fujiwara, Takashi Takeuchi, Yu Otake, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kove Univ) ICD2008-127 |
We propose a novel substrate-bias control scheme for FD-SOI SRAM that suppresses inter-die variability and achieves low-... [more] | ICD2008-127 pp.131-136 |
| ICD | 2006-04-13 10:45 |
Oita | Oita University | [Special Invited Talk]
Sub-1V DRAM Design Takayuki Kawahara (Hitachi Central Research Lab.) |
Issues for sub-1V DRAM operation and its solutions are described. Since the low voltage operation of DRAM is difficult,... [more] | ICD2006-4 pp.19-24 |
| EE | 2005-07-22 15:40 |
Kyoto | Sub-1V Power Supply System with Variable-stage SC-type DC-DC Converter Scheme for Ambient Energy Sources Yoshihumi Yoshida, Humiyasu Utsunomiya (Seiko Instruments), Takakuni Douseki (NTT) |
This paper describes a sub-1-V power-supply, which is useful for self-powered short-range wireless systems with ambient ... [more] | EE2005-30 pp.103-108 |
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| ICD | 2004-12-16 10:00 |
Hiroshima | Dynamic-Vth, Dual-Power-Supply SRAM Cell Using D2G-SOI for Low-Power SoC Application Masanao Yamaoka, Kenichi Osada, Kiyoo Itoh, Ryuta Tsuchiya, Takayuki Kawahara (Hitachi, Ltd.) |
We developped two SRAM memory cells suitable for low-power SoC. The memory cells are composed of new FD-SOI transistors,... [more] | ICD2004-183 pp.1-5 |
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