Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD |
2023-03-01 11:00 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Measured Evaluation of BTI Degradation in a 65nm FDSOI Process using Ring Oscillators with Same Circuit Structure Daisuke Kikuta (KIT), Ryo Kishida (TPU), Kazutoshi Kobayashi (KIT) VLD2022-73 HWS2022-44 |
(To be available after the conference date) [more] |
VLD2022-73 HWS2022-44 pp.1-6 |
VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 14:00 |
Online |
Online (Online) |
Measurement Results of Total Ionizing Dose Effect on Ring Oscillators Fabricated by a Thin-BOX FDSOI Process for Outer-space Mission Takashi Yoshida, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2020-30 ICD2020-50 DC2020-50 RECONF2020-49 |
The Total Ionizing Dose (TID) effect is one of the major concerns for semiconductor devices in outer space, where high a... [more] |
VLD2020-30 ICD2020-50 DC2020-50 RECONF2020-49 pp.110-114 |
SDM, ICD, ITE-IST [detail] |
2018-08-07 11:30 |
Hokkaido |
Hokkaido Univ., Graduate School of IST M Bldg., M151 (Hokkaido) |
Comparison of Sensitivity to Soft Errors of NMOS and PMOS Transistors by Using Three Types of Stacking Latches in an FDSOI process Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) SDM2018-28 ICD2018-15 |
(To be available after the conference date) [more] |
SDM2018-28 ICD2018-15 pp.15-20 |
VLD, HWS (Joint) |
2018-02-28 17:20 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103 |
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] |
VLD2017-103 pp.85-90 |
VLD, HWS (Joint) |
2018-02-28 17:45 |
Okinawa |
Okinawa Seinen Kaikan (Okinawa) |
Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104 |
Moore's Law has been miniaturizing integrated circuits, which
can make a lot of high performance devices such as PCs an... [more] |
VLD2017-104 pp.91-96 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus (Osaka) |
Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43 |
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more] |
VLD2016-49 DC2016-43 pp.31-36 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:40 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus (Osaka) |
Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44 |
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] |
VLD2016-50 DC2016-44 pp.37-41 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 15:05 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus (Osaka) |
Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-51 DC2016-45 |
We evaluate tolerance for soft errors of FFs on a 28/65 nm FDSOI. We fabricated three different layouts of non-redundant... [more] |
VLD2016-51 DC2016-45 pp.43-48 |