| IEICE Technical Committee Submission System Conference Schedule |
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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, ICD, VLD | 2025-03-05 - 2025-03-08 |
Okinawa | (Okinawa, Online) (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
A Study on SQA Acceleration Using Multi-FPGA for Route Optimization of Large-scale Mobile Robots System Thinh NguyenQuang, Kosuke Matsuyama (Tohoku University), Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp Corporation), Hasitha Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki (Tohoku University) |
(To be available after the conference date) [more] | |
| VLD, RECONF | 2025-01-16 10:30 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
 VLD2024-79 RECONF2024-109 |
(To be available after the conference date) [more] | VLD2024-79 RECONF2024-109 pp.18-22 |
| VLD, RECONF | 2025-01-16 10:55 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
An FPGA Implementation of Object Tracking System using Center of Mass Computation with Integral Images Yusuke Hara, Shinji Fukuma (Fukui Univ) VLD2024-80 RECONF2024-110 |
(To be available after the conference date) [more] | VLD2024-80 RECONF2024-110 pp.23-28 |
| VLD, RECONF | 2025-01-16 11:20 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Stabilization Techniques for Online Computation-Oriented Linear Equation Solvers Targeting FPGA Implementation Yuma Omoto, Yuya Shuto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) VLD2024-81 RECONF2024-111 |
(To be available after the conference date) [more] | VLD2024-81 RECONF2024-111 pp.29-34 |
| VLD, RECONF | 2025-01-16 15:05 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Efficient FPGA Implementation of Compressor Trees Based on Generalized Parallel Counter Chains Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2024-84 RECONF2024-114 |
(To be available after the conference date) [more] | VLD2024-84 RECONF2024-114 pp.47-52 |
| VLD, RECONF | 2025-01-16 16:10 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
VLD2024-86 RECONF2024-116 |
(To be available after the conference date) [more] | VLD2024-86 RECONF2024-116 pp.59-63 |
| VLD, RECONF | 2025-01-16 16:35 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
VLD2024-87 RECONF2024-117 |
(To be available after the conference date) [more] | VLD2024-87 RECONF2024-117 pp.64-68 |
| VLD, RECONF | 2025-01-17 09:00 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
A design hackathon aimed at sparking interest in semiconductors with an AI application Takao Goto, Mizuho Nitami, Hideharu Amano, Atsutake Kosuge, Yuki Mitarai, Jiawei Yu, Yuxuan PAN, Makoto Ikeda (The Univ. of Tokyo) VLD2024-88 RECONF2024-118 |
(To be available after the conference date) [more] | VLD2024-88 RECONF2024-118 pp.69-74 |
| VLD, RECONF | 2025-01-17 11:20 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
CNN accelerator using Winograd algorithm Kota Saito, Cong-Kha Pham (UEC) VLD2024-93 RECONF2024-123 |
(To be available after the conference date) [more] | VLD2024-93 RECONF2024-123 pp.95-98 |
| VLD, RECONF | 2025-01-17 14:20 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Emulation Environment for Reconfigurable Virtual Accelerator (ReVA) with QEMU Kaoru Kayukawa, Shunya Kawai, Kazuki Yaguchi (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo, LCC.), Hironori Nakajo (TUAT) VLD2024-96 RECONF2024-126 |
(To be available after the conference date) [more] | VLD2024-96 RECONF2024-126 pp.110-115 |
| VLD, RECONF | 2025-01-17 15:10 |
Kanagawa | Yokohama Technology Campus Flagship Building (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Proposal and evaluation of Heterostructure Clusters Using PAE Cells for eFPGA IP Tatsuya Sasaki, Ryo Iwasaki, Kensyu Seto, Masahiro Iida (Kumamoto Univ.) VLD2024-98 RECONF2024-128 |
(To be available after the conference date) [more] | VLD2024-98 RECONF2024-128 pp.122-127 |
| DC | 2024-12-06 16:15 |
Oita | Southern Cross Community Square (Oita) | Development of a Level Crossing Controller with Train Moving Direction Detection Function and Its Condition Monitoring Haruki Araie, Hiroshi Mochizuki, Hideo Nakamura (Nihon Univ.) DC2024-103 |
At present, railway signaling systems in which control information is transmitted via track circuits (rails) have been d... [more] | DC2024-103 pp.25-28 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-12 15:35 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
FPGA Implementation of Multiplication-Free Table-Lookup-Based CNN Accelerator Hiroshi Fuketa, Toshihiro Katashita, Yohei Hori, Masakazu Hioki (AIST) VLD2024-34 ICD2024-52 DC2024-56 RECONF2024-64 |
In this paper, a table lookup-based computing technique is proposed to perform convolutional neural network (CNN) infere... [more] | VLD2024-34 ICD2024-52 DC2024-56 RECONF2024-64 pp.43-48 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 16:00 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
A Low-Cost Point Cloud Deep Learning Model Using Neural ODE for FPGAs Mizuki Yasuda, Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) VLD2024-55 ICD2024-73 DC2024-77 RECONF2024-85 |
(To be available after the conference date) [more] | VLD2024-55 ICD2024-73 DC2024-77 RECONF2024-85 pp.159-164 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-13 16:40 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Development of generative AI-based automated design technology for AI chips Yasutaka Serizawa, Hisanori Matsumoto (Hitachi) VLD2024-59 ICD2024-77 DC2024-81 RECONF2024-89 |
As the shortage of human resources for advanced AI / IT techniques accelerates, while the application of AI chips (GPUs,... [more] | VLD2024-59 ICD2024-77 DC2024-81 RECONF2024-89 pp.183-187 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-14 09:00 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Implementation and Performance Evaluation of an FPGA-Based Electronic Circuit Simulator with a Speculative Execution Linear Solver using Gauss-Jordan Elimination and the BiCGSTAB Method Yuya Shuto, Yuma Omoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) VLD2024-62 ICD2024-80 DC2024-84 RECONF2024-92 |
To accelerate electronic circuit simulation, we propose a speculative execution linear solver that combines the Gauss-Jo... [more] | VLD2024-62 ICD2024-80 DC2024-84 RECONF2024-92 pp.198-203 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2024-11-14 09:25 |
Oita | COMPAL HALL (Oita, Online) (Primary: On-site, Secondary: Online) |
Proposal for NV of Logic Cell Architecture for eFPGA IP Keizo Hiraga (SSS), Kensu Seto, Masahiro Iida (Kumamoto Univ), Kazuhiro Bessho (SSS) VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93 |
As eFPGAs (embedded FPGAs) are required to shift from hard IP to soft IP, we propose to make a new programmable logic ce... [more] | VLD2024-63 ICD2024-81 DC2024-85 RECONF2024-93 pp.204-209 |
| SR, RCS (Joint) (2nd) |
2024-11-04 - 2024-11-07 |
Overseas | Fraunhofer IPT (Overseas) | [Poster Presentation]
An FPGA-based CNN Accelerator for Wireless Physical Layer Martin Lastovka (M.Sc. Student), Mohsen Pourghasemian (Research Assistant), Firooz Saghezchi (PhD), Haris Gacanin (Professor) |
Convolutional Neural Networks (CNNs) can handle different tasks such as channel estimation in wireless Physical Layer (P... [more] | |
| HWS, ICD | 2024-11-01 11:15 |
Aomori | Hirosaki University (Aomori, Online) (Primary: On-site, Secondary: Online) |
Calculation of Target Transfer Function of Side Channel Leakage Path Based on Power Supply Noise Simulation Rei Mitsuyasu, Masaki Himuro, Kengo Iokibe, Yoshitaka Toyota (Okayama Univ.) HWS2024-62 ICD2024-33 |
There is a risk that crytopgraphic keys can be disclosed from hardware implementations of cryptography such as AES by si... [more] | HWS2024-62 ICD2024-33 pp.1-6 |
| HWS, ICD | 2024-11-01 17:30 |
Aomori | Hirosaki University (Aomori, Online) (Primary: On-site, Secondary: Online) |
Secret Sharing Supporting Multi-input gates on FPGA Design for Less Communication Bandwidth Network Yinfan Zhao, Makoto Ikeda (UTokyo) HWS2024-73 ICD2024-44 |
Multi-Party Computation (MPC) is a cryptographic technology that enables multiple participants to collaboratively comput... [more] | HWS2024-73 ICD2024-44 pp.59-64 |
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