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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 462  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SANE 2023-06-30
Kanagawa JAXA Sagamihara Campus
(Primary: On-site, Secondary: Online)
Study of implementation of on-board SAR with FPGA
Hiroai Asami (Mitsubishi Electric Corp.)
(To be available after the conference date) [more]
RECONF 2023-06-09
Kochi Eikokuji Campus, Kochi University of Technology
(Primary: On-site, Secondary: Online)
A Study of Quantum Computing-Oriented Large-Scale Memory Computation Directly Connected to NVM Storages: Parallel Implementation and Evaluation of Serial ATA Interface on an FPGA
Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi (Univ. of Tsukuba), Hideharu Amano, Wei Kaijie (Keio Univ.) RECONF2023-9
(To be available after the conference date) [more] RECONF2023-9
NLP, MSS 2023-03-16
(Primary: On-site, Secondary: Online)
[Invited Talk] Social Applications of FPGA and Machine Learning
Yuichiro Shibata, Taito Manabe (Nagasaki Univ.) MSS2022-87 NLP2022-132
A field programmable gate array (FPGA) is a programmable device that allows users to configure logic circuits at their h... [more] MSS2022-87 NLP2022-132
RCC, ISEC, IT, WBS 2023-03-14
(Primary: On-site, Secondary: Online)
FPGA implementation of PQC Signature Algorithm QR-UOV using High Level Synthesis
Kimihiro Yamakoshi, Tsunekaze Saito (NTT) IT2022-92 ISEC2022-71 WBS2022-89 RCC2022-89
QR-UOV has been proposed by Furue et al. as a signature scheme with security tolerance gainst quantum computers. QR-UOV... [more] IT2022-92 ISEC2022-71 WBS2022-89 RCC2022-89
HWS, VLD 2023-03-01
(Primary: On-site, Secondary: Online)
Large-scale SAT Solution Search by FPGA Implementation of Attraction-Repulsion Control-Type Amoeba Algorithm
Torao Okuyama (Keio Univ.), Masashi Aono, Kaori Okoda (Amoeba Energy), Hideharu Amano (Keio Univ.) VLD2022-82 HWS2022-53
(To be available after the conference date) [more] VLD2022-82 HWS2022-53
HWS, VLD 2023-03-03
(Primary: On-site, Secondary: Online)
Study of Intrinsic ID extracted from RG-DTM Arbiter PUF implemented on FPGA
Mika Sakai, Tatsuya Oyama, Kota Yoshida (Ritsumeikan Univ.), Yohei Hori, Toshihiro Katashita (AIST), Masayoshi Shirahata, Takeshi Fujino (Ritsumeikan Univ.) VLD2022-111 HWS2022-82
We studied the implementation method of PUF for generating a unique ID on FPGA. We adopted a method of controlling the p... [more] VLD2022-111 HWS2022-82
HWS, VLD 2023-03-04
(Primary: On-site, Secondary: Online)
Importance of Inverters Placement in Ring-Oscilator for Laser Irradiation Detection
Shungo Hayashi (YNU), Junichi Sakamoto (AIST/YNU), Masaki Chikano, Tsutomu Matsumoto (YNU) VLD2022-115 HWS2022-86
Laser fault injection is known as the most efficient fault injection technique due to its high spatial controllability a... [more] VLD2022-115 HWS2022-86
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] VLD2022-56 RECONF2022-79
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-24
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Efficient FPGA Implementation of Binarized Neural Networks Based on Generalized Parallel Counter Tree
Takahiro Tanigawa, Mugi Noda, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2022-68 RECONF2022-91
Binarized neural networks (BNN) allow compact hardware implementation by binarizing weight values and neuron activations... [more] VLD2022-68 RECONF2022-91
DC 2022-12-16
(Primary: On-site, Secondary: Online)
Stuck-at Fault Tolerance in DNN Using Outliers and Sampling
Tomohiro Ishii, Kazuteru Namba (Chiba Univ.) DC2022-75
The development of artificial intelligence and the expansion of big data have led to the implementation of neural networ... [more] DC2022-75
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
(Primary: On-site, Secondary: Online)
FPGA Implementation and Area Evaluation of JTAG Access Mechanism Using Lightweight One-Time Password Authentication Scheme
Hisashi Okamoto, Jun Ma, Senling Wang, Hiroshi Kai, Hiroshi Takahashi (Ehime Univ), Akihiro Shimizu (Kochi Univ. of Technology) VLD2022-48 ICD2022-65 DC2022-64 RECONF2022-71
When building a cyber-physical system (CPS), it is essential to guarantee the fault tolerance and security of edge devic... [more] VLD2022-48 ICD2022-65 DC2022-64 RECONF2022-71
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2022-11-30
(Primary: On-site, Secondary: Online)
FPGA Implementation of Learned Image Compression
Heming Sun (Waseda U), Qingyang Yi (UTokyo), Jiro Katto (Waseda U), Masahiro Fujita (UTokyo) VLD2022-53 ICD2022-70 DC2022-69 RECONF2022-76
Learned image compression (LIC) has reached a superior coding gain than traditional hand-crafted standards such as JPEG ... [more] VLD2022-53 ICD2022-70 DC2022-69 RECONF2022-76
RECONF 2022-09-07
(Primary: On-site, Secondary: Online)
Efficient Learning of Spiking Neural Networks with Genetic Algorithm and its FPGA Acceleration
Taiki Watanabe, Yukinori Sato (TUT) RECONF2022-26
Spiking Neural Network (SNN) is one of the promising models of neuromorphic architecture. A learning method using a gene... [more] RECONF2022-26
CPSY, DC, IPSJ-ARC [detail] 2022-07-28
Yamaguchi Kaikyo Messe Shimonoseki
(Primary: On-site, Secondary: Online)
Preliminary evaluation of "SLMLET" chip with RISC-V MP and SLM reconfigurable logic
Yosuke Yanai (Keio Univ.), Takuya Kojima (Tokyo Univ.), Hayate Okuhara (NUS.), Masahiro Iida (Kumamoto Univ.), Hideharu Amano (Keio Univ.) CPSY2022-8 DC2022-8
In recent years, processing power in IoT edge devices has been further improved. Therefore, a solution called a mixed FP... [more] CPSY2022-8 DC2022-8
EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] 2022-07-19
Online Online Security Evaluation of Cryptographic Circuits with Laser Sensors by Double-Spot Laser Irradiation
Masaki Chikano, Naoki Yoshida, Junichi Sakamoto, Syungo Hayashi, Tsutomu Matsumoto (YNU) ISEC2022-16 SITE2022-20 BioX2022-41 HWS2022-16 ICSS2022-24 EMM2022-24
A fault injection attack is an attack method that intentionally injects faults into a device to cause it to malfunction,... [more] ISEC2022-16 SITE2022-20 BioX2022-41 HWS2022-16 ICSS2022-24 EMM2022-24
SIS, IPSJ-AVM 2022-06-09
Fukuoka KIT(Wakamatsu Campus)
(Primary: On-site, Secondary: Online)
Hardware Implementation of Annealing Machine using Chaotic Boltzmann Machine
Kanta Yoshioka (Kyutech), Ichiro Kawashima, Hakaru Tamukoh (Kyutech/Neumorph Center) SIS2022-1
With the end of Moore's law, annealing quantum computers that can solve various combinatorial optimization problems are ... [more] SIS2022-1
SIS, IPSJ-AVM 2022-06-10
Fukuoka KIT(Wakamatsu Campus)
(Primary: On-site, Secondary: Online)
[Tutorial Lecture] How to build a High-Precision and Efficient Robot Vision: Dataset Generation and Hardware Implementation for Deep Learning
Hakaru Tamukoh (Kyutech) SIS2022-10
This tutorial lecture explains a construction method for high-precision and efficient robot vision that includes a semi-... [more] SIS2022-10
RECONF 2022-06-07
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Hardware implementation of the protocol for ROS2 and robot modules without CPU
Daiki Matsunaga, Tomoya Shoji, Shozo Takeoka (AXE) RECONF2022-3
ROS2 is a set of software libraries and tools for robot applications. It is widely used in robot development. A ROS2 rob... [more] RECONF2022-3
RECONF 2022-06-07
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Preliminary Evaluation of FPGA-to-FPGA Communication Speed in FPGA Cluster ESSPER
Rintaro Sakai, Yasuhiro Nakahara (Kumamoto Univ. /R-CSS), Kentaro Sano (R-CCS), Masahiro Iida (Kumamoto Univ. /R-CSS) RECONF2022-11
This study evaluates the communication speed between FPGAs assuming the FPGA cluster ESSPER is a scalable and
flexible ... [more]
RECONF 2022-06-08
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)
Investigation of methods to accelerate inference processing by deep learning
Seiya Iwamoto, Chikako Nakanishi (OIT) RECONF2022-13
AI technologies such as deep learning are generally computationally intensive and have very high performance requirement... [more] RECONF2022-13
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