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 Results 1 - 6 of 6  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:25
Kochi Kochi University of Technology Side Channel Security of an FPGA Pairing Implementation with Pipelined Modular Multiplier
Mitsufumi Yamazaki, Junichi Sakamoto, Yuta Okuaki, Tsutomu Matsumoto (YNU) ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
Since bilinear pairing is useful in realizing advanced cryptography, side channel security evaluation of its high-speed ... [more] ISEC2019-29 SITE2019-23 BioX2019-21 HWS2019-24 ICSS2019-27 EMM2019-32
pp.151-156
ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] 2019-07-23
14:50
Kochi Kochi University of Technology An FPGA Implementation of Aggregate Signature Schemes with Pipelined Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33
Expectations for "Advanced Cryptography" are increasing in order to enhance the security of cyber physical systems and c... [more] ISEC2019-30 SITE2019-24 BioX2019-22 HWS2019-25 ICSS2019-28 EMM2019-33
pp.157-162
HWS, ICD 2018-10-29
14:30
Osaka Kobe Univ. Umeda Intelligent Laboratory An Acceleration of Compressed Squaring for Pairing Implementation with Pipeline Modular Multiplier
Yota Okuaki, Junichi Sakamoto, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matsumoto (YNU) HWS2018-50 ICD2018-42
One of the biggest problems of the emerging cyber-physical and cloud computing systems is how to ensure security with en... [more] HWS2018-50 ICD2018-42
pp.19-24
HWS 2018-04-13
13:55
Fukuoka   Energy Evaluation of FPGA Pairing Implementation with Pipeline Modular Multiplier
Yusuke Nagahama, Daisuke Fujimoto, Junichi Sakamoto, Tsutomu Matsumoto (YNU) HWS2018-5
Energy consumption and latency are important features of dedicated hardware bilinear pairing calculators. However publi... [more] HWS2018-5
pp.23-28
HWS
(2nd)
2017-09-15
16:55
Tokyo   An FPGA Implementation of Optimal Ate Pairing Hardware using Pipeline Type Modular Multiplier for BN Curve over 254 bit Prime Field
Yusuke Nagahama (YNU), Daisuke Fujimoto (NAIST), Tsutomu Matsumoto (YNU)
(To be available after the conference date) [more]
RECONF 2008-05-22
14:15
Fukushima The University of Aizu FPGA Implementation of Elliptic Curve Arithmetic in Characteristic Five by High-level Synthesis
YoungKwang Moon (Tokyo Univ.), Hideyuki Tsuchiya, Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ.) RECONF2008-4
The Tate pairing, which is a mapping on elliptic curves, has been
applied to many cryptographic protocols such as a tri... [more]
RECONF2008-4
pp.19-24
 Results 1 - 6 of 6  /   
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