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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 32  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
SDM, ICD, ITE-IST [detail] 2023-08-02
14:00
Hokkaido Hokkaido Univ. Multimedia Education Bldg. 3F
(Primary: On-site, Secondary: Online)
[Invited Talk] Technology Trends in CMOS Devices for Advanced Logic LSIs -- FinFET, BS-PDN, GAA-NS-FET, CFET, 2D-CFET --
Hitoshi Wakabayashi (Tokyo Tech) SDM2023-46 ICD2023-25
Technology Trends in CMOS Devices are going to be discussed for Advanced Logic LSIs. [more] SDM2023-46 ICD2023-25
pp.50-55
ICD 2023-04-10
11:25
Kanagawa
(Primary: On-site, Secondary: Online)
ICD2023-3 (To be available after the conference date) [more] ICD2023-3
p.8
MW, ED 2019-01-17
16:25
Tokyo Hitachi, Central Research Lab. [Invited Talk] Silicon Semiconductor, "past, present, and future"
Shin'ichiro Kimura (Hitachi) ED2018-80 MW2018-147
(To be available after the conference date) [more] ED2018-80 MW2018-147
pp.63-66
SDM 2018-01-30
14:00
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Reliability and Scalability of FinFET Split-Gate MONOS Array with Tight Vth Distribution for 16/14nm-node Embedded Flash
Shibun Tsuda, Tomoya Saito, Hirokazu Nagase, Yoshiyuki Kawashima, Atsushi Yoshitomi, Shinobu Okanishi, Tomohiro Hayashi, Takuya Maruyama, Masao Inoue, Seiji Muranaka, Shigeki Kato, Takuya Hagiwara, Hirokazu Saito, Tadashi Yamaguchi, Masaru Kadoshima, Takahiro Maruyama, Tatsuyoshi Mihara, Hiroshi Yanagita, Kenichiro Sonoda, Tomohiro Yamashita, Yasuo Yamaguchi (renesas) SDM2017-94
Reliability and scalability of split-gate metal-oxide nitride oxide silicon (SG-MONOS) are discussed for 16/14nm-node em... [more] SDM2017-94
pp.13-16
ICD, CPSY, CAS 2017-12-14
15:10
Okinawa Art Hotel Ishigakijima Function Evaluation of Adiabatic FinFET SRAM with Virtual Ground Structure
Rintaro Itoh, Yasuhiro Takahashi, Toshikazu Sekine (Gifu Univ.) CAS2017-89 ICD2017-77 CPSY2017-86
The SRAM discussed in this paper is a 10T-SRAM that reduces the leakage current in hold mode by using the virtual ground... [more] CAS2017-89 ICD2017-77 CPSY2017-86
pp.119-122
SDM 2017-10-25
16:00
Miyagi Niche, Tohoku Univ. Nanoscale conformal doping technology by spin on diffusion source
Tetsuro Kinoshita, Shunichi Mashita, Takuya Ohashi, Yoshihiro Sawada, Yohei Kinoshita, Satoshi Fujimura (TOK) SDM2017-53
We developed a coating material which can form nanoscale conformal film on the wafer with 3D structure. In this study, c... [more] SDM2017-53
pp.21-24
ICD 2017-04-20
14:55
Tokyo   [Invited Lecture] First demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and beyond
Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) ICD2017-7
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] ICD2017-7
pp.35-38
ICD 2017-04-20
15:20
Tokyo   [Invited Talk] Embedded Flash Technology for Automotive Applications
Masaya Nakano, Takashi Ito, Tadaaki Yamauchi, Yasuo Yamaguchi, Takashi Kono, Hideto Hidaka (Renesas Electronics) ICD2017-8
Higher fuel-efficient engine and advanced driver assistance system (ADAS) require the further progress of embedded Flash... [more] ICD2017-8
pp.39-44
SDM 2017-01-30
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] First Demonstration of FinFET Split-Gate MONOS for High-Speed and Highly-Reliable Embedded Flash in 16/14nm-node and Beyond
Shibun Tsuda, Yoshiyuki Kawashima, Kenichiro Sonoda, Atsushi Yoshitomi, Tatsuyoshi Mihara, Shunichi Narumi, Masao Inoue, Seiji Muranaka, Takahiro Maruyama, Tomohiro Yamashita, Yasuo Yamaguchi (Renesas Electronics), Digh Hisamoto (Hitachi) SDM2016-134
FinFET split-gate metal-oxide nitride oxide silicon (SG-MONOS) Flash memories have been fabricated and operated for the ... [more] SDM2016-134
pp.17-20
VLD, DC, CPSY, RECONF, CPM, ICD, IE
(Joint) [detail]
2016-11-28
14:40
Osaka Ritsumeikan University, Osaka Ibaraki Campus Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] VLD2016-50 DC2016-44
pp.37-41
EID, SDM 2015-12-14
11:00
Kyoto Ryukoku University, Avanti Kyoto Hall Fabrication of FinFET Structure with High Selectivity Etching Using Newly Developed SiNx Etch Gas
Takashi Kojiri (Tohoku Univ./ZEON), Tomoyuki Suwa, Keiichi Hashimoto, Akinobu Teramoto, Rihito Kuroda, Shigetoshi Sugawa (Tohoku Univ.) EID2015-9 SDM2015-92
We evaluated the properties of newly developed SiNx etch gas (SSY525). The gas indicated high selectivity as 30 ~ 60 for... [more] EID2015-9 SDM2015-92
pp.1-4
SDM 2015-01-27
15:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Accurate Prediction of PBTI Lifetime in N-type Fin-Channel High-k Tunnel FETs
Wataru Mizubayashi, Takahiro Mori, Koichi Fukuda, Yongxun Liu, Takashi Matsukawa, Yuki Ishikawa, Kazuhiko Endo, Shinichi Ohuchi, Junichi Tsukada, Hiromi Yamauchi, Yukinori Morita, Shinji Migita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2014-143
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k ... [more] SDM2014-143
pp.33-36
SDM 2015-01-27
15:55
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] 16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM Macros with Wordline Overdriven Assist
Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka, Koji Tanaka, Miki Tanaka, Koji Nii (Renesas) SDM2014-144
We demonstrate 16 nm FinFET High-k/Metal-gate SRAM macros with a wordline (WL) overdriven read/write-assist circuit. Tes... [more] SDM2014-144
pp.37-40
SDM 2015-01-27
16:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Experimental Realization of Complementary p- and n- Tunnel FinFETs with Subthreshold Slopes of Less than 60 mV/decade and Very Low (pA/um) Off-Current on a Si CMOS Platform
Yukinori Morita, Takahiro Mori, Koichi Fukuda, Wataru Mizubayashi, Shinji Migita, Takashi Matsukawa, Kazuhiko Endo, Shinichi O'uchi, Yongxun Liu, Meishoku Masahara, Hiroyuki Ota (AIST) SDM2014-146
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very... [more] SDM2014-146
pp.45-48
ICD 2014-04-18
13:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Multigate FinFET Device and Circuit Technology for 10nm and Beyond
Meishoku Masahara, Kazuhiko Endo, Shin-ichi Ouchi, Takashi Matsukawa, Yongxun Liu, Shinji Migita, Wataru Mizubayashi, Yukinori Morita, Hiroyuki Ota (AIST) ICD2014-15
One of the biggest challenges for the VLSI circuits with 20-nm-technology nodes and beyond is to overcome the issue of a... [more] ICD2014-15
pp.77-82
SDM 2014-01-29
10:50
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Heated Ion Implantation Technology for Highly Reliable Metal-gate/High-k CMOS SOI FinFETs
Wataru Mizubayashi (AIST), Hiroshi Onoda, Yoshiki Nakashima (Nissin Ion Equipment), Yuki Ishikawa, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shinichi Ouchi, Junichi Tsukada, Hiromi Yamauchi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Meishoku Masahara (AIST) SDM2013-138
The impact of heated ion implantation (I/I) technology on metal-gate (MG)/high-k (HK) CMOS SOI FinFET performance and re... [more] SDM2013-138
pp.13-16
SDM, ED
(Workshop)
2012-06-29
11:15
Okinawa Okinawa Seinen-kaikan [Invited Talk] Thermal-Aware Device Desing of Nanoscale MOS Transistors
Ken Uchida (Keio Univ.), Tsunaki Takahashi, Nobuyasu Beppu (Tokyo Tech)
The self-heating effects in Bulk/SOI FinFETs have been systematically investigated and compared. It is demonstrated that... [more]
ICD 2012-04-24
14:50
Iwate Seion-so, Tsunagi Hot Spring (Iwate) Device-Conscious Circuit Designs for 0.5-V High-Speed Nanoscale CMOS LSIs
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya (Hitachi), Masashi Horiguchi (Renesas) ICD2012-15
The feasibility of 0.5-V memory-rich nanoscale CMOS LSIs was studied. First, nanoscale fully-depleted MOSFETs (FD MOS) a... [more] ICD2012-15
pp.79-84
ICD 2011-04-19
10:55
Hyogo Kobe University Takigawa Memorial Hall 0.5-V FinFET SRAM Using Dynamic-Threshold-Voltage Pass Gates
Shin-ichi O'uchi, Kazuhiko Endo, Yongxun Liu, Takashi Matsukawa, Tadashi Nakagawa, Yuki Ishikawa, Junichi Tsukada, Hiromi Yamauchi, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST) ICD2011-11
This article presents a FinFET SRAM which salvages malfunctioned bits caused by random variation. In the presenting SRAM... [more] ICD2011-11
pp.59-63
SDM, ED 2011-02-23
16:30
Hokkaido Hokkaido Univ. A Study on Precise FinFET High Frequency Characteristic Evaluation Method
Hideo Sakai (Keio Univ.), Shinichi Ouchi, Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Junichi Tsukada, Yuki Ishikawa, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Kunihiro Sakamoto, Meishoku Masahara (AIST), Hiroki Ishikuro (Keio Univ.) ED2010-198 SDM2010-233
In recent years, different research groups have been focusing on FinFET transistor research as an excellent replacement ... [more] ED2010-198 SDM2010-233
pp.37-42
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