IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 133  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
ICD 2024-04-12
10:45
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Talk] Recent Developments and Challenges for NAND Flash Memory Interface
Takashi Toi (KIOXIA)
(To be available after the conference date) [more]
ICD 2024-04-12
13:25
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Lecture] 5-Bit/2Cell(X2.5), 7-Bit/2Cell(X3.5), 9-Bit/2Cell(X4.5) NAND Flash Memory: Half Bit technology
Noboru Shibata, Hironori Uchikawa, Taira Shibuya, Kenri Nakai, Kosuke Yanagidaira, Kosuke Yanagidaira (KIOXIA)
(To be available after the conference date) [more]
SDM 2024-01-31
13:35
Tokyo KIT Toranomon Graduate School
(Primary: On-site, Secondary: Online)
[Invited Talk] CMOS Directly Bonded to Array (CBA) Technology for Future 3D Flash Memory
Masayoshi Tagami (KIOXIA) SDM2023-76
3D stacked devices have been developed and manufactured to realize gains in power, performance, area and cost (PPAC) in ... [more] SDM2023-76
pp.9-12
SDM 2023-10-13
14:30
Miyagi Niche, Tohoku Univ. [Invited Talk] Determination of charge centroid location and energy depth of charge carriers trapped in silicon nitride charge-trap layers
Kiyoteru Kobayashi (Tokai Univ.) SDM2023-56
Metal-oxide-nitride-oxide-semiconductor (MONOS) field-effect transistors have been employed for memory cells in three-di... [more] SDM2023-56
pp.13-20
ICD 2023-04-11
11:00
Kanagawa
(Primary: On-site, Secondary: Online)
[Invited Talk] 1 Tb 4b/Cell 176-Tier 3D NAND Flash with 4 Independent Planes for Read
Tomoharu Tanaka (MMJ) ICD2023-9
In the presentation, a 1Tb 4b/cell 3D-NAND-Flash memory on a 176-tier technology with a 14.7Gb/mm2 bit density is shown ... [more] ICD2023-9
p.17
ICD, SDM, ITE-IST [detail] 2022-08-08
11:45
Online   [Invited Talk] Optimal Cell Structure/Operation Design of 3D Semicircular Split-gate Cells for Ultra-high-density Flash Memory
Tetsu Morooka, , , , , , , , , , , , , , , , , , , , , , , , (Kioxia) SDM2022-36 ICD2022-4
Control gate split cell structure for increasing the cell density by foot-print reduction has several challenges such as... [more] SDM2022-36 ICD2022-4
p.12
SDM 2020-01-28
15:45
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Future of Non-Volatile Memory - From Storage to Computing
Kazunari Ishimaru (kioxia) SDM2019-87
More than thirty years passed since the first NAND flash memory was presented at the IEDM. The NAND flash memory expande... [more] SDM2019-87
p.19
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
09:40
Ehime Ehime Prefecture Gender Equality Center Device characteristic measurement for realizing CMOS-compatible non-volatile memory using FiCC
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2019-36 DC2019-60
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] VLD2019-36 DC2019-60
pp.63-68
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
14:15
Ehime Ehime Prefecture Gender Equality Center Neural Network-based Lifetime Prediction and Reliability Enhancement Techniques for 3D NAND Flash Memory
Masaki Abe, Ken Takeuchi (Chuo Univ.) ICD2019-30 IE2019-36
NAND flash memories have lifetime such as data-retention time and read cycles. This paper proposes neural network techni... [more] ICD2019-30 IE2019-36
pp.7-12
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-15
15:45
Ehime Ehime Prefecture Gender Equality Center Design of optimal NV-memory configuration for hybrid SSD with QLC NAND flash memory
Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi (Chuo Univ.) ICD2019-41 IE2019-47
In order to expand capacity and reduce cost of NAND flash memory, the number of bits per cell has been increased. Howeve... [more] ICD2019-41 IE2019-47
pp.59-63
LQE, OPE, CPM, EMD, R 2019-08-22
16:45
Miyagi   [Invited Talk] 3D Flash Memory Cell Reliability
Yuichiro Mitani, Harumi Seki, Takanori Asano, Yasushi Nakasaki (Toshiba Memory) R2019-26 EMD2019-24 CPM2019-25 OPE2019-53 LQE2019-31
As conventional planar NAND flash memories are limited from physical and electrical scaling point of view, the three-dim... [more] R2019-26 EMD2019-24 CPM2019-25 OPE2019-53 LQE2019-31
pp.35-38
SDM, ICD, ITE-IST [detail] 2019-08-07
16:30
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and [Invited Talk] High-temperature stable Physical Unclonable Functions with error-free readout scheme based on 28nm SGMONOS flash memory for security applications
Takahiro Shimoi, Tomoya Saito, Hirokazu Nagase, Masayuki Izuna, Akihiko Kanda, Takashi Ito, Takashi Kono (Renesas Electronics) SDM2019-39 ICD2019-4
Highly reliable Physical Unclonable Functions (PUF) based on 28nm Split-Gate MONOS (SG-MONOS) embedded flash memory is d... [more] SDM2019-39 ICD2019-4
pp.15-19
SDM, ICD, ITE-IST [detail] 2019-08-08
09:15
Hokkaido Hokkaido Univ., Graduate School /Faculty of Information Science and [Invited Talk] *
Tetsufumi Tanamoto (Teikyo Univ.) SDM2019-40 ICD2019-5
The development of quantum annealing machines (QAMs) based on superconducting qubits
has progressed considerably in re... [more]
SDM2019-40 ICD2019-5
pp.21-26
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
09:00
Hiroshima Satellite Campus Hiroshima Design and fabrication of characteristics measurement circuit for CMOS-compatible ultra-low-power non-volatile memory element using FiCC
Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) VLD2018-65 DC2018-51
This report proposes a new non-volatile memory element that can be fabricated with a standard CMOS process, and that can... [more] VLD2018-65 DC2018-51
pp.183-188
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-07
13:45
Hiroshima Satellite Campus Hiroshima Autonomous SCM capacity adjustment method in SCM/NAND flash hybrid storage
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) CPM2018-94 ICD2018-55 IE2018-73
Performance of hybrid storage with storage class memory (SCM) and NAND flash memory is improved by using SCM as non-vola... [more] CPM2018-94 ICD2018-55 IE2018-73
pp.29-30
DC, SS 2018-10-04
14:25
Aichi Inuyama City Kokusai-Kanko Center Freud Multi-stage Error Collection Adaptive for Reliability in NAND Flash Memory
Ryo Ogura, Masato Kitakami (Chiba Univ.) SS2018-19 DC2018-20
 [more] SS2018-19 DC2018-20
pp.7-12
SDM, ICD, ITE-IST [detail] 2018-08-08
15:00
Hokkaido Hokkaido Univ., Graduate School of IST M Bldg., M151 Study of new stacked type logic circuit with fabrication technology of 3D NAND flash memory -- Comparison with conventional LUT scheme, and planar typescheme --
Fumiya Suzuki, Sigeyoshi Watanabe (Shonan Inst. of Tech.) SDM2018-43 ICD2018-30
Novel new stacked type logic circuit with fabrication technology of 3D flash memory has been newly proposed. Also, These... [more] SDM2018-43 ICD2018-30
pp.95-100
ICD 2018-04-19
10:35
Tokyo   Application-optimized heterogeneously-integrated storage with non-volatile memories
Chihiro Matsui, Ken Takeuchi (Chuo Univ.) ICD2018-2
Data center storages require application-optimized heterogeneous integration of non-volatile memories. Two types of stor... [more] ICD2018-2
pp.7-10
ICD 2018-04-20
11:10
Tokyo   [Invited Talk] A 512Gb 3b/Cell 3D Flash Memory on a 96-Word-Line-Layer Technology
Hiroshi Maejima, Kazushige Kanda, Susumu Fujimura, Teruo Takagiwa, Susumu Ozawa, Jumpei Sato, Yoshihiko Shindo, Manabu Sato, Naoaki Kanagawa, Junji Musha, Satoshi Inoue, Katsuaki Sakurai, Toshifumi Hashimoto (TMC), Hao Nguyen, Ken Cheah, Hiroshi Sugawara, Seungpil Lee (WDC), Toshiki Hisada, Tetsuya Kaneko, Hiroshi Nakamura (TMC) ICD2018-10
A 512Gb 3b/cell flash has been developed on a 96-WL-layer BiCS FLASH technology. This work implements three key technolo... [more] ICD2018-10
pp.39-44
SDM 2018-01-30
13:30
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Lateral Charge Migration Suppression Technique of 3D-NAND Flash by Vth Nearing
Kyoji Mizoguchi, Shohei Kotaki, Yoshiaki Deguchi, Ken Takeuchi (Chuo Univ.) SDM2017-93
In the near data computing, a SSD controller embeds more processing units and RAMs to execute a part of application whic... [more] SDM2017-93
pp.9-12
 Results 1 - 20 of 133  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan