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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] | 2023-11-16 10:20 |
Kumamoto | Civic Auditorium Sears Home Yume Hall (Primary: On-site, Secondary: Online) |
Proposal of MTJ-based non-volatile flip-flops using reference resistance and Two-step Store Control Kousei Kaizu, Kimiyoshi Usami (SIT)  VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 |
Non-Volatile Flip Flops (NVFF) using Magnetic Tunnel Junction (MTJ) enable non-volatile power gating and reduce leakage ... [more] | VLD2023-45 ICD2023-53 DC2023-52 RECONF2023-48 pp.88-93 |
| CPSY, DC, IPSJ-ARC [detail] | 2023-08-03 11:45 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
Design of soft-error tolerant non-volatile flip-flops Shogo Takahashi, Kazuteru Namba (Chiba Univ.) CPSY2023-13 DC2023-13 |
In recent years，the incidence of soft errors in VLSI has been increasing due to miniaturization，higher integration，and l... [more] | CPSY2023-13 DC2023-13 pp.31-36 |
| ICD | 2023-04-10 09:55 |
Kanagawa | (Primary: On-site, Secondary: Online) |
[Invited Lecture]
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations Yuki Abe, Kazutoshi Kobayashi (KIT), Jun Shiomi (Osaka Univ.), Hiroyuki Ochi (Ritsumeikan Univ.) ICD2023-1 |
Energy harvesting is a key technology to supply power for Internet of Things (IoT) devices. Computing devices for IoTs m... [more] | ICD2023-1 pp.1-6 |
| VLD, HWS [detail] | 2022-03-07 14:05 |
Online | Online | Measurement Results of Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations Yuki Abe, Kazutoshi Kobayashi (KIT), Hiroyuki Ochi (Ritsumeikan Univ.) VLD2021-85 HWS2021-62 |
In recent years, with the spread of the Internet of Things (IoT) and mobile devices, low power consumption of processors... [more] | VLD2021-85 HWS2021-62 pp.45-50 |
| VLD, DC, RECONF, ICD, IPSJ-SLDM (Joint) [detail] |
2020-11-18 14:00 |
Online | Online | Physically Unclonable Functions(PUF) curcuit using Non-Volatile Flip-Flop and security evaluation against modeling attacks Hiroki Ishihara, Kimiyoshi Usami (Shibaura IT) VLD2020-37 ICD2020-57 DC2020-57 RECONF2020-56 |
In recent years, imitative LSIs have become a serious problem and security technology PUF to use manufacturing variabili... [more] | VLD2020-37 ICD2020-57 DC2020-57 RECONF2020-56 pp.139-144 |
| HWS, VLD [detail] | 2020-03-04 13:00 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
MTJ-based Nonvolatile Flip-Flop Circuit Using Dual Power Supplies for Low-voltage Operation Sosuke Akiba, Kimiyoshi Usami (SIT) VLD2019-99 HWS2019-72 |
One of the leakage reduction techniques is nonvolatile power gating(NVPG) by using magnetic tunnel junction(MTJ). In the... [more] | VLD2019-99 HWS2019-72 pp.31-36 |
| SCE | 2020-01-17 13:15 |
Kanagawa | [Poster Presentation]
Design and evaluation of single flux quantum circuits by using local magnetic flux bias technique Shunta Asada, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2019-42 |
We developed a local magnetic flux bias (LFB) technique to introduce a phase shift in the superconducting circuit. The L... [more] | SCE2019-42 pp.53-56 |
|
| DC | 2019-02-27 15:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Improvement of Flip-Flop Performance Considering the Influence of Power Supply Noise Yuya Kinoshita, Yukiya Miura (Tokyo Metropolitan Univ.) DC2018-82 |
With the scaling down and low-power operation of VLSI circuits, influence on circuit behavior by power supply noise such... [more] | DC2018-82 pp.67-72 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2018-12-07 09:25 |
Hiroshima | Satellite Campus Hiroshima | Flip-Flops with different retention characteristics for process variation estimation Kento Fukazawa, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ.) VLD2018-66 DC2018-52 |
This paper proposes to use multiple D-Flip-Flops having different retention characteristics with Ring Oscillator to moni... [more] | VLD2018-66 DC2018-52 pp.189-193 |
| VLD, HWS (Joint) |
2018-02-28 17:20 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103 |
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] | VLD2017-103 pp.85-90 |
| VLD, HWS (Joint) |
2018-02-28 17:45 |
Okinawa | Okinawa Seinen Kaikan | Evaluation of Soft Error Tolerance on Flip-Flop depending on 65 nm FDSOI Transistor Threshold-Voltage Mitsunori Ebara, Haruki Maruoka, Kodai Yamada, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-104 |
Moore's Law has been miniaturizing integrated circuits, which can make a lot of high performance devices such as PCs an... [more] |
VLD2017-104 pp.91-96 |
| VLD, HWS (Joint) |
2018-03-02 10:30 |
Okinawa | Okinawa Seinen Kaikan | Implementation of Reconfigurable Accelerator Cool Mega-Array Using MTJ-based Nonvolatile Flip-Flop Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami, Masaru Kudo (SIT), Hideharu Amano, Takeharu Ikezoe (Keio Univ.), Keizo Hiraga, Yusuke Shuto, Kojiro Yagami (Sony SS) VLD2017-122 |
As a method of reducing the power consumption of the flip-flop circuit, there is a nonvolatile flip-flop (NVFF) that ena... [more] | VLD2017-122 pp.199-204 |
| DC | 2018-02-20 16:35 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Influence on Flip-Flop Behaviors by Power Supply Noise and Proposal of their Countermeasures Miyuki Inoue, Yukiya Miura (Tokyo Metropolitan Univ.) DC2017-88 |
With the scaling down and low power operation of VLSI circuits, effects on circuit behavior by power supply noise such a... [more] | DC2017-88 pp.67-72 |
| VLD | 2017-03-01 14:25 |
Okinawa | Okinawa Seinen Kaikan | A Nonvolatile Flip-Flop Circuit with a Split Store/Restore Architecture for Power Gating Masaru Kudo, Kimiyoshi Usami (Shibaura Institute of Tech.) VLD2016-103 |
This paper describes a nonvolatile Flip-Flop (NVFF) circuit to implement Nonvolatile Power Gating. We proposed a new NVF... [more] | VLD2016-103 pp.7-12 |
| CPSY, RECONF, VLD, IPSJ-SLDM, IPSJ-ARC [detail] | 2017-01-25 10:15 |
Kanagawa | Hiyoshi Campus, Keio Univ. | MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data Junya Akaike, Kimiyoshi Usami (SIT) VLD2016-97 CPSY2016-133 RECONF2016-78 |
With the spread of portable devices in recent year, products with high performance and low power consumption are require... [more] | VLD2016-97 CPSY2016-133 RECONF2016-78 pp.175-180 |
| DC | 2016-02-17 16:05 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Study on the Effect of Power Supply Noise on Flip-Flop Circuits Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) DC2015-96 |
According to the scaling down, and lower power design of VLSI circuits, power supply noise such as IR-drop affects the o... [more] | DC2015-96 pp.61-66 |
| LQE, EST, OPE, EMT, PN, MWP, IEE-EMT, PEM [detail] | 2016-01-29 11:15 |
Hyogo | Proposal of Optical Flip-Flop Operation Among Different Phase States with SOA and Feedback Loop Takahiro Kamidai, Kenta Takase, Hiroki Kishikawa, Nobuo Goto, Shin-ichiro Yanagiya (Tokushima Univ.) PN2015-101 EMT2015-152 OPE2015-214 LQE2015-201 EST2015-158 MWP2015-127 |
A flip-flop circuit between two phase states is proposed and analyzed. The flip-flop circuit consists of an SOA, two dir... [more] | PN2015-101 EMT2015-152 OPE2015-214 LQE2015-201 EST2015-158 MWP2015-127 pp.405-410 |
|
| ICD | 2015-04-17 13:30 |
Nagano | [Invited Lecture]
A 2.4 pJ Ferroelectric-Based Non-Volatile Flip-Flop with 10-Year Data Retention Capability Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori (ROHM), Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.) ICD2015-11 |
A ferroelectric-based (FE-based) non-volatile flip-flop (NVFF) is proposed for low-power LSI. Since leakage current in ... [more] |
ICD2015-11 pp.51-55 |
|
| SDM, EID | 2014-12-12 14:00 |
Kyoto | Kyoto University | Characterization of Synchronous and Asynchronous Circuits using poly-Si TFTs Yosuke Nagase (Ryukoku Univ.), Tokiyoshi Matsuda, Mutsumi Kimura (Osaka Univ.), Taketoshi Matsumoto, Hikaru Kobayashi (Ryukoku Univ.) EID2014-25 SDM2014-120 |
We have evaluated multiple-input NAND circuits using polycrystalline silicon thin-film transistors and found that the ou... [more] | EID2014-25 SDM2014-120 pp.61-65 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 09:15 |
Oita | B-ConPlaza | Design of Flip-Flop with Timing Error Tolerance Taito Suzuki, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (SIT), Masao Yanagisawa (Waseda Univ.) VLD2014-79 DC2014-33 |
Under the influence of the miniaturization of the integrated circuit, the variation of the operation condition of the ci... [more] | VLD2014-79 DC2014-33 pp.45-50 |
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