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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-01 13:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT)  VLD2022-76 HWS2022-47 |
Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vec... [more] | VLD2022-76 HWS2022-47 pp.19-24 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
[Invited Talk]
Can we say "No FPGA, No Smart City"? Hiroaki Nishi (Keio Univ.) VLD2022-60 RECONF2022-83 |
From the perspective of a chair of standardization of technologies related to Smart City information infrastructure, we ... [more] | VLD2022-60 RECONF2022-83 p.24 |
| HWS, ICD | 2022-10-25 15:40 |
Shiga | (Primary: On-site, Secondary: Online) |
Hardware Acceleration of TFHE-based Adder by Controlling Error Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32 |
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] | HWS2022-40 ICD2022-32 pp.58-63 |
| NS | 2022-04-15 13:25 |
Tokyo | kikai shinkou kaikan + online (Primary: On-site, Secondary: Online) |
Study of Multi-access VPN Systems with Hardware Accelerators Katsuma Miyamoto, Hiroki Kano, Koji Sugisono, Shinya Kawano (NTT) NS2022-5 |
In recent years, the use of VPN services has increased rapidly due to the spread of telework, and the use of VPN service... [more] | NS2022-5 pp.25-30 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 15:35 |
Online | Online | Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80 |
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] | VLD2021-72 CPSY2021-41 RECONF2021-80 pp.132-137 |
| SDM, ICD, ITE-IST [detail] | 2021-08-18 13:00 |
Online | Online | [Invited Talk]
A 12nm autonomous driving processor running 60.4 TOPS and 13.8 TOPS/W CNNs with task-separated ASIL D control Katsushige Matsubara, Lieske Hanno (Renesas Electronics), Motoki Kimura (Renesas Electronics Europe), Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei (Renesas Electronics) SDM2021-39 ICD2021-10 |
Next-generation driver assistance systems and automated driving systems require both high performances to realize enormo... [more] | SDM2021-39 ICD2021-10 pp.48-53 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| HWS, VLD [detail] | 2021-03-04 14:15 |
Online | Online | Experiments of Data Authenticity Verification in Multi-Node IoT Systems Using Elliptic Curve Digital Signature Chips Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.) VLD2020-85 HWS2020-60 |
Practicality of IoT systems requires the efficiency and speed of crypto processing in edge nodes and remote servers. So ... [more] | VLD2020-85 HWS2020-60 pp.97-101 |
| CPSY, RECONF, VLD, IPSJ-ARC, IPSJ-SLDM [detail] | 2021-01-25 15:15 |
Online | Online | A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) VLD2020-49 CPSY2020-32 RECONF2020-68 |
In recent years, CNN has been used for various tasks in the field of computer vision and has achievedexcellent performan... [more] | VLD2020-49 CPSY2020-32 RECONF2020-68 pp.58-62 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| RCS, AP (Joint) |
2018-11-22 11:20 |
Okinawa | Okinawa Industry Support Center | Hardware Accelerator for Coordinated Radio-Resource Scheduling in 5G Ultra-high-density Distributed Antenna Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu (NTT) RCS2018-208 |
This paper presents a novel radio-resource scheduler with a hardware accelerator for coordinated scheduling in 5G ultra-... [more] | RCS2018-208 pp.173-178 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| CS | 2017-07-27 13:45 |
Nagasaki | Fukue Bunka Kaikan | [Invited Talk]
A Study on Application of Hardware Accelerator for Radio-resource Scheduler in 5G Mobile Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) CS2017-24 |
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] | CS2017-24 pp.53-58 |
| RCS | 2017-06-21 16:35 |
Okinawa | Ishigaki Shoukou Kaikan | Hardware Accelerator for Radio-Resource Scheduling in Ultra-high Dense Distributed Antenna Systems Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura (NTT) RCS2017-58 |
For the fifth generation mobile communication systems (5G), in order to increase overall system throughput, ultra-high-d... [more] | RCS2017-58 pp.49-54 |
| VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-30 13:45 |
Osaka | Ritsumeikan University, Osaka Ibaraki Campus | Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis Daisuke Ishikawa, Kenshu Seto (TCU) VLD2016-69 DC2016-63 |
We propose data transfer optimization in accelerator design with high-level synthesis. Typical accelerator designs perfo... [more] | VLD2016-69 DC2016-63 pp.147-152 |
| NS | 2016-10-20 13:50 |
Hyogo | Himeji Nishi-Harima Area Jibasan Center | Distributed Packet Processing Architecture using Hardware Accelerators for 100Gbps Forwarding Throughput on Virtualized Edge Router Satoshi Nishiyama, Hitoshi Kaneko, Ichiro Kudo (NTT) NS2016-90 |
To implement virtualized service edge functions on carrier networks by general-purpose servers, it is necessary to impro... [more] | NS2016-90 pp.13-18 |
| RECONF | 2016-05-19 10:45 |
Kanagawa | FUJITSU LAB. | Design of an FPGA-based Accelerator for Moleculer Dynamics Using OpenCL Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Kota Kasahara (Osaka Univ.) RECONF2016-4 |
Molecular dynamics (MD) simulations are very important to study physical properties of atoms and molecules. However, a h... [more] | RECONF2016-4 pp.13-16 |
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