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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| NS, IN (Joint) |
2024-03-01 14:15 |
Okinawa | Okinawa Convention Center | A Study of Power Consumption Reduction by Dynamic Hardware Offload in Virtualized Base Stations Riichiro Nagareda, Chikara Sasaki, Atsushi Tagami (KDDI Research), Tomohiro Otani (KDDI)  IN2023-103 |
Sixth-generation (6G) mobile communication systems have been studied to deal with the exponential increase in mobile tr... [more] |
IN2023-103 pp.225-230 |
| VLD, HWS, ICD | 2024-02-29 11:15 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design of RISC-V SoC with Post-quantum Encryption Algorithm Acceleration Jiyuan Xin, Makoto Ikeda (UTokyo) VLD2023-110 HWS2023-70 ICD2023-99 |
The foundational elements of the Internet of Things (IoT) are increasingly intricate and robust Systems-on-Chips (SoCs) ... [more] | VLD2023-110 HWS2023-70 ICD2023-99 pp.66-71 |
| VLD, HWS, ICD | 2024-03-02 10:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Design of General Hardware for Optimal Strategy in Isogeny-Based Post-Quantum Cryptography Kosei Nakamura, Makoto Ikeda (UT) VLD2023-137 HWS2023-97 ICD2023-126 |
The computation in isogeny-based post-quantum cryptography primarily consists of two operations: scalar multiplication o... [more] | VLD2023-137 HWS2023-97 ICD2023-126 pp.198-203 |
| RECONF, VLD | 2024-01-30 13:20 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97 |
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] | VLD2023-94 RECONF2023-97 pp.81-86 |
| RECONF, VLD | 2024-01-30 14:50 |
Kanagawa | AIRBIC Meeting Room 1-4 (Primary: On-site, Secondary: Online) |
FPGA-Accelerated Random Forest for Real-Time IoT Intrusion Detection Qingyu Zeng, Yuko Hara (Tokyo Tech) VLD2023-97 RECONF2023-100 |
The rapid proliferation of the Internet of Things (IoT) has heightened cyber security concerns, necessitating efficient ... [more] | VLD2023-97 RECONF2023-100 pp.99-104 |
| IE, CS, IPSJ-AVM [detail] | 2023-12-11 15:30 |
Fukuoka | Kyushu Institute of Technology (Primary: On-site, Secondary: Online) |
[Special Invited Talk]
High-Performance Image Processing Utilizing Hardware Norishige Fukushima (nitech) CS2023-83 IE2023-25 |
High-speed image signal processing is important to realize applications in various environments. To complete image proc... [more] |
CS2023-83 IE2023-25 p.16 |
| NS | 2023-10-04 14:55 |
Hokkaido | Hokkaidou University + Online (Primary: On-site, Secondary: Online) |
Study of high availability VPN gateway with hardware accelerator Kotomi Takahashi, Katsuma Miyamoto, Hiroki kano, Shinya Kawano, Yasuyuki matsuoka (NTT) NS2023-75 |
In recent years, the amount of VPN (Virtual Private Network) traffic has been increasing due to the spread of teleworkin... [more] | NS2023-75 p.29 |
| RECONF | 2023-09-14 16:10 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA) Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) RECONF2023-21 |
In this paper，we propose a simulation environment using Post-Implementation Simulation of Vivado to confirm functions of... [more] | RECONF2023-21 pp.11-12 |
| RECONF | 2023-09-14 16:40 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24 |
Vector processors can load lots of data and perform operations in parallel. The Vector Register Sharing Mechanism, prop... [more] |
RECONF2023-24 pp.18-19 |
| RECONF | 2023-09-15 13:25 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29 |
Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] | RECONF2023-29 pp.40-45 |
| RECONF | 2023-09-15 13:50 |
Tokyo | Tokyo University of Agriculture and Technology Koganei campus (Primary: On-site, Secondary: Online) |
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) RECONF2023-30 |
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] | RECONF2023-30 pp.46-51 |
| RECONF | 2023-08-04 14:55 |
Hokkaido | Hakodate Arena (Primary: On-site, Secondary: Online) |
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo) RECONF2023-15 |
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] | RECONF2023-15 pp.7-12 |
| HWS, VLD | 2023-03-01 13:25 |
Okinawa | (Primary: On-site, Secondary: Online) |
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT) VLD2022-76 HWS2022-47 |
Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vec... [more] | VLD2022-76 HWS2022-47 pp.19-24 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA) Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80 |
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] | VLD2022-57 RECONF2022-80 pp.7-12 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 13:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
[Invited Talk]
Can we say "No FPGA, No Smart City"?
-- Let's declare if we do a smart city, we need FPGAs. -- Hiroaki Nishi (Keio Univ.) VLD2022-60 RECONF2022-83 |
From the perspective of a chair of standardization of technologies related to Smart City information infrastructure, we ... [more] | VLD2022-60 RECONF2022-83 p.24 |
| HWS, ICD | 2022-10-25 15:40 |
Shiga | (Primary: On-site, Secondary: Online) |
Hardware Acceleration of TFHE-based Adder by Controlling Error Yinfan Zhao, Ikeda Makoto (Univ. of Tokyo) HWS2022-40 ICD2022-32 |
Fully homomorphic encryption (FHE) is expected to be used in the secure delegating computation. The bootstrapping in the... [more] | HWS2022-40 ICD2022-32 pp.58-63 |
| NS | 2022-04-15 13:25 |
Tokyo | kikai shinkou kaikan + online (Primary: On-site, Secondary: Online) |
Study of Multi-access VPN Systems with Hardware Accelerators Katsuma Miyamoto, Hiroki Kano, Koji Sugisono, Shinya Kawano (NTT) NS2022-5 |
In recent years, the use of VPN services has increased rapidly due to the spread of telework, and the use of VPN service... [more] | NS2022-5 pp.25-30 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-25 15:35 |
Online | Online | Preliminary evaluation of cache coherent interconnect for Reconfigurable Virtual Accelerator (ReVA) Eriko Maeda, Daichi Teruya, Hironori Nakajo (TUAT) VLD2021-72 CPSY2021-41 RECONF2021-80 |
In recent years, the amount of computation and data in HPC, AI, and other computational processing has become increasing... [more] | VLD2021-72 CPSY2021-41 RECONF2021-80 pp.132-137 |
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