| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, HWS [detail] | 2022-03-08 11:25 |
Online | Online | A Method for Automatic Test Pattern Generation using an SMT Solver for HDL Code Ryoichi Isawa, Nobuyuki Kanaya, Yoshitada Fujiwara, Tatsuta Takehisa, Hayato Ushimaru, Dai Arisue, Daisuke Makita, Satoshi Mimura, Daisuke Inoue (NICT)  VLD2021-95 HWS2021-72 |
(To be available after the conference date) [more] | VLD2021-95 HWS2021-72 pp.105-110 |
| CAS, CS | 2022-03-04 13:45 |
Online | Online | Evaluation of Trojan Detector for AI Hardware Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) CAS2021-94 CS2021-96 |
In recent years, AI edge computing has been expanding to realize real-time inference by implementing AI models on edge d... [more] | CAS2021-94 CS2021-96 pp.106-111 |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 11:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] | VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
| RECONF | 2018-09-18 14:50 |
Fukuoka | LINE Fukuoka Cafe Space | Data Flow Representation and its Applications to Machine Learning Accelerator Kazuki Nakada (Tsukuba Univ. of Tech.), Keiji Miura (Kwansei Gakuin Univ.) RECONF2018-32 |
Researches and development of machine learning accelerators have been rapidly progressing. It is becoming important to r... [more] | RECONF2018-32 pp.73-78 |
| NS, IN (Joint) |
2018-03-01 11:30 |
Miyazaki | Phoenix Seagaia Resort | A study of feasibility evaluation for performance estimation on network hardware abstraction Yuki Takei, Satoshi Nishiyama, Saki Hatta, Koji Yamazaki (NTT) NS2017-186 |
When deploying the network functions at optimal positions by using the hardware devices such as CPU, FPGA and NPU, it is... [more] | NS2017-186 pp.109-112 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 16:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Integrated Machine Code Monitor on FPGA Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) VLD2017-73 CPSY2017-117 RECONF2017-61 |
Machine code monitor is necessary for initial program development stage when implementing a new processor with unique IS... [more] | VLD2017-73 CPSY2017-117 RECONF2017-61 pp.65-70 |
| VLD | 2016-02-29 15:00 |
Okinawa | Okinawa Seinen Kaikan | High-Level Synthesis of Embedded Systems Controller from Erlang Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2015-114 |
This article presents a method of specifying the behavior of embedded systems' control by a subset of Erlang and synthes... [more] | VLD2015-114 pp.19-24 |
| RECONF | 2015-09-18 13:25 |
Ehime | Ehime University | Design of Hardware Description Language FSL Based on Object-Oriented/Functional Programming Languages Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2015-37 |
This paper presents a new hardware description language FSL. The FSL inherits the design philosophy and the language fea... [more] | RECONF2015-37 pp.27-32 |
| SS | 2015-05-11 15:40 |
Kumamoto | Kumamoto University | Classification of Code Clones in Hardware Description Language Kyohei Uemura, Kenji Fujiwara, Hajimu Iida (NAIST) SS2015-5 |
With the growth of the electric circuit size and complexity, Hardware Description Language (HDL) is widely used in hardw... [more] | SS2015-5 pp.23-28 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita | B-ConPlaza | A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] | VLD2014-82 DC2014-36 pp.81-86 |
| EMCJ, IEE-EMC, MW, EST [detail] | 2013-10-24 15:45 |
Miyagi | Tohoku Univ. | Design of an FPGA-Based FDTD Accelerator Using OpenCL Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.) EMCJ2013-73 MW2013-113 EST2013-65 |
High-performance computing systems with dedicated hardware on FPGAs can achieve power efficient computations compared wi... [more] | EMCJ2013-73 MW2013-113 EST2013-65 pp.73-76 |
| CPSY | 2013-10-03 10:45 |
Chiba | Makuhari Messe | Design of a translator to Verilog HDL from hardware modeling language ArchHDL Shimpei Sato, Kenji Kise (Tokyo Inst. of Tech.) CPSY2013-31 |
We have proposed ArchHDL as a new language for hardware RTL modeling. In ArchHDL, we realized continuous assignment and ... [more] | CPSY2013-31 pp.1-6 |
| RECONF | 2011-09-26 14:20 |
Aichi | Nagoya Univ. | Development Modeling Compiler and Operation Test for the Hardware Design Generate HDL from UML State Machine Diagram Daiki Kano, Ryota Yamazaki (Tokai Univ.), Naohiko Shimizu (Tokai Univ./IP ARCH, Inc.) RECONF2011-27 |
This paper describes the UML modeling compiler and operation test using that．The UML modeling compiler performs automati... [more] | RECONF2011-27 pp.31-36 |
| RECONF, VLD, CPSY, IPSJ-SLDM [detail] | 2011-01-18 10:55 |
Kanagawa | Keio Univ (Hiyoshi Campus) | Feasibility of JHDL for Dynamically Reconfigurable Hardware Design Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) VLD2010-103 CPSY2010-58 RECONF2010-72 |
To develop applications for dynamically reconfigurable hardware, the description language which increases the efficienc... [more] | VLD2010-103 CPSY2010-58 RECONF2010-72 pp.133-138 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2010-11-30 13:15 |
Fukuoka | Kyushu University | A case study of the effective value range analysis for Behavioral synthesis Kenji Tomonaga, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2010-32 |
The digital circuit becomes more complex and larger scale recently, and behavioral synthesis that use behavioral descri... [more] |
CPSY2010-32 pp.1-6 |
| RECONF | 2009-09-18 09:50 |
Tochigi | Utsunomiya Univ. | Comparison and Evaluation of Application Implementation Methods for Dynamically Reconfigurable Processor DAPDNA-2 Naomichi Furushima, Nobuya Watanabe, Akira Nagoya (Okayama Univ) RECONF2009-30 |
Design tools are essential to implement applications on dynamically reconfigurable hardware efficiently, therefore to un... [more] | RECONF2009-30 pp.67-72 |
| NC | 2008-11-08 10:30 |
Saga | Saga Univ. | Automatic generation of self organizing map hardware Akira Onoo (Oita Univ.), Hiroomi Hikawa (Kansai Univ.) NC2008-65 |
This paper discusses the development of hardware Self-Organizing Map (SOM) generator, which generates VHSIC Hardware Des... [more] | NC2008-65 pp.37-42 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2008-01-17 17:15 |
Kanagawa | Hiyoshi Campus, Keio University | Hardware Consious Style: a C Language Style for Hardware Design Kaiyi Mao, Hideharu Amano, Satoshi Tsutsumi, Vasutan Tunbunheng (Keio Univ.) VLD2007-135 CPSY2007-78 RECONF2007-81 |
In order to cope with recent complicated functions in multi-media applications, C-based behavioral design method has bee... [more] | VLD2007-135 CPSY2007-78 RECONF2007-81 pp.101-106 |
| SIP, CAS, CS | 2007-03-06 09:30 |
Tottori | Blancart Misasa (Tottori) | [Poster Presentation]
Cost Optimization Using Tabu Search in Hardware Design of Arbitrary Functions Koji Kotani, Takao Sasaki, Hisamichi Toyoshima (Kanagawa Univ.) CAS2006-95 SIP2006-196 CS2006-112 |
In digital circuit design using a hardware description language, some elementary functions and user defined functions ca... [more] | CAS2006-95 SIP2006-196 CS2006-112 pp.15-18 |
| NS, OCS (Joint) |
2007-01-26 13:00 |
Miyazaki | A Study on Buffer Control Mechanism Guaranteeing Various Delay-Bandwidth Requirements in Broadband Router Hideki Tode, Rie Fujita, Yusuke Shinohara, Koso Murakami (Osaka Univ.) NS2006-154 |
In this paper, to provide the enhanced QoS for various applications, we extensively propose new QoS control mechanism b... [more] |
NS2006-154 pp.19-24 |
|
[Return to Top Page]