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All Technical Committee Conferences  (Searched in: Recent 10 Years)

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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 67  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ICD, VLD 2025-03-06
15:55
Okinawa (Okinawa, Online)
(Primary: On-site, Secondary: Online)
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo)
 [more]
DC 2025-02-18
14:40
Tokyo Kikai-Shinko-Kaikan Bldg. (Tokyo) An Approach to High-Level Synthesis with Hard Error Resilience
Asahi Noma, Satoshi Ohtake (Oita Univ.) DC2024-112
(To be available after the conference date) [more] DC2024-112
pp.37-42
VLD, RECONF 2025-01-16
11:20
Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Stabilization Techniques for Online Computation-Oriented Linear Equation Solvers Targeting FPGA Implementation
Yuma Omoto, Yuya Shuto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) VLD2024-81 RECONF2024-111
This paper proposes a method for developing linear solvers using High-Level Synthesis (HLS), specifically designed for o... [more] VLD2024-81 RECONF2024-111
pp.29-34
VLD, RECONF 2025-01-16
15:30
Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Hardware Design Using Python for Full Hardware Implementation of RTOS-Based Systems
Hikaru Shiga, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2024-85 RECONF2024-115
This paper proposes a method for describing hardware design and testing using Python in the context of a technique that ... [more] VLD2024-85 RECONF2024-115
pp.53-58
VLD, RECONF 2025-01-17
14:45
Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Development of Self-Calibration Hardware Interface for a Peripheral on Super General Purpose SoC
Hibiki Shinozaki, Akira Yamawaki (KIT) VLD2024-97 RECONF2024-127
Super general purpose SoC (System on chip) has dedicated hardware interfaces for all peripherals and dynamically reconfi... [more] VLD2024-97 RECONF2024-127
pp.116-121
DC 2024-12-06
14:25
Oita Southern Cross Community Square (Oita) A Method of Register Binding for synthesis for diagnosability
Shuji Kubokura, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Masayosi Yoshimura (KSU) DC2024-99
In fault diagnosis, it is important to increase the number of distinguishable fault pairs to improve the diagnostic reso... [more] DC2024-99
pp.7-12
SIS, ITE-BCT 2024-10-04
11:00
Hokkaido Hokusei Gakuen Univ. (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Development of single frame sprite drawing hardware in High-level Synthesis
Yuka Otani, Akira Yamawaki (Kyutech) SIS2024-25
As part of a hardware-oriented game library created using high-level synthesis, the development of hardware capable of d... [more] SIS2024-25
pp.47-52
CPSY, DC, RECONF, IPSJ-ARC [detail] 2024-08-09
17:50
Tokushima Awagin Hall (Tokushima, Online)
(Primary: On-site, Secondary: Online)
CPSY2024-40 DC2024-40 RECONF2024-40 This paper describes automatic circuit partitioning method for multi-FPGAs with high-level synthesis. First, A multi-FPG... [more] CPSY2024-40 DC2024-40 RECONF2024-40
pp.135-140
SIS 2024-06-06
15:20
Hiroshima Hiroshima University (Hiroshima, Online)
(Primary: On-site, Secondary: Online)
Development of sprite drawing hardware combining high-level synthesis and FPGA internal memory
Keigo Aoki, Akira Yamawaki (Kyutech) SIS2024-6
Mobile terminals are required to have higher performance and functionality while conserving even more power. To realize ... [more] SIS2024-6
pp.29-34
SIS 2024-06-06
16:30
Hiroshima Hiroshima University (Hiroshima, Online)
(Primary: On-site, Secondary: Online)
Hardware Implementation of Calibration Data Loading Part in Device Driver for an SPI Peripheral
Hibiki Shinozaki, Akira Yamawaki (Kyutech) SIS2024-9
Device drivers that control SPI devices will not be able to maximize their performance due to software overhead. In this... [more] SIS2024-9
pp.45-49
VLD, HWS, ICD 2024-03-01
14:00
Okinawa (Okinawa, Online)
(Primary: On-site, Secondary: Online)
High-Level Synthesis Method for Python Considering Runtime Profiling
Yusuke Suzuki, Makoto Ikeda (UTokyo) VLD2023-127 HWS2023-87 ICD2023-116
With the increasing complexity of LSI design in recent years, high-level synthesis (HLS) technology has attracted attent... [more] VLD2023-127 HWS2023-87 ICD2023-116
pp.145-150
RECONF, VLD 2024-01-30
13:20
Kanagawa AIRBIC Meeting Room 1-4 (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Reduction of Circuit Size by Optimizing Status Registers in Full Hardware RTOS-Based Systems
Kei Mikami, Nagisa Ishiura (Kansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2023-94 RECONF2023-97
This article presents a technique for handling increased number of tasks by reducing both circuit size and critical path... [more] VLD2023-94 RECONF2023-97
pp.81-86
RECONF, VLD 2024-01-30
13:45
Kanagawa AIRBIC Meeting Room 1-4 (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Implementation of External Memory Access for Binary Synthesis Using General-Purpose High-Level Synthesizer
Sho Kishimoto, Nagisa Ishiukra (Kwansei Gakuin Univ.) VLD2023-95 RECONF2023-98
In this article, we present a method for implementing external memory access within the context of binary synthesis util... [more] VLD2023-95 RECONF2023-98
pp.87-92
ICTSSL, CAS 2024-01-25
11:00
Kanagawa (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Performance effect of memory access pattern for high-level synthesized sprite drawing hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-85 ICTSSL2023-38
We are developing a sprite drawing hardware suitable for high-level synthesis. Sprite drawing stores the sprite image in... [more] CAS2023-85 ICTSSL2023-38
pp.17-22
SIS 2023-12-07
11:00
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] SIS2023-24
pp.1-6
SIS 2023-12-07
11:20
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Development of a real-time non-photorealistic rendering system with a high-level synthesized pencil drawing style image conversion hardware
Honoka Tani, Akira Yamawaki (Kyutech) SIS2023-25
We developed non-photorealistic rendering (NPR) libraries optimized for high-level synthesis (HLS) technology that autom... [more] SIS2023-25
pp.7-12
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-16
14:10
Kumamoto Civic Auditorium Sears Home Yume Hall (Kumamoto, Online)
(Primary: On-site, Secondary: Online)
Hardware obfuscation method using Obfuscator-LLVM and Bambu
Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.) VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57
Hardware obfuscation serves as a countermeasure against hardware reverse engineering. Yamada et al. employed the OLLVM s... [more] VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57
pp.125-130
MSS, CAS, SIP, VLD 2023-07-06
09:30
Hokkaido (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Performance Improvement by Integrating Former and Latter Processes of Pencil Drawing Style Image Conversion on High-Level Synthesized Hardware.
Honoka Tani, Akira Yamawaki (Kyutech) CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1
We are developing hardware to realize a high-performance and low-power embedded image processing device using high-level... [more] CAS2023-1 VLD2023-1 SIP2023-17 MSS2023-1
pp.1-5
MSS, CAS, SIP, VLD 2023-07-06
10:10
Hokkaido (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
pp.10-15
RECONF 2023-06-08
16:00
Kochi Eikokuji Campus, Kochi University of Technology (Kochi, Online)
(Primary: On-site, Secondary: Online)
Parallelization of Prim's Algorithm Using FPGA and Its Performance Evaluation
Noritsune O, Kenji Kanazawa, Moritoshi Yasunaga (Univ. of Tsukuba) RECONF2023-3
A subgraph of an undirected graph G that is connected and contains no closed paths is called a tree, a global tree is a ... [more] RECONF2023-3
pp.13-16
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