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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 13 of 13  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
HWS, ICD, VLD 2025-03-06
15:55
Okinawa (Okinawa, Online)
(Primary: On-site, Secondary: Online)
Single-Source Shortest Path FPGA Accelerator Using Multiple Parallel Searches with High-Level Synthesis and Linked List Implementation
Haopeng Meng, Kazutoshi Wakabayashi, Makoto Ikeda (The University of Tokyo)
 [more]
VLD, RECONF 2025-01-16
11:20
Kanagawa Yokohama Technology Campus Flagship Building (Kanagawa, Online)
(Primary: On-site, Secondary: Online)
Stabilization Techniques for Online Computation-Oriented Linear Equation Solvers Targeting FPGA Implementation
Yuma Omoto, Yuya Shuto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) VLD2024-81 RECONF2024-111
This paper proposes a method for developing linear solvers using High-Level Synthesis (HLS), specifically designed for o... [more] VLD2024-81 RECONF2024-111
pp.29-34
SIS, ITE-BCT 2024-10-04
11:00
Hokkaido Hokusei Gakuen Univ. (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Development of single frame sprite drawing hardware in High-level Synthesis
Yuka Otani, Akira Yamawaki (Kyutech) SIS2024-25
As part of a hardware-oriented game library created using high-level synthesis, the development of hardware capable of d... [more] SIS2024-25
pp.47-52
VLD, HWS, ICD 2024-03-01
14:00
Okinawa (Okinawa, Online)
(Primary: On-site, Secondary: Online)
High-Level Synthesis Method for Python Considering Runtime Profiling
Yusuke Suzuki, Makoto Ikeda (UTokyo) VLD2023-127 HWS2023-87 ICD2023-116
With the increasing complexity of LSI design in recent years, high-level synthesis (HLS) technology has attracted attent... [more] VLD2023-127 HWS2023-87 ICD2023-116
pp.145-150
SIS 2023-12-07
11:00
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Data Path Parallelization to Improve Performance of High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) SIS2023-24
A mobile terminal architecture which can dynamically reconfigure the optimal hardware for each application can achieve h... [more] SIS2023-24
pp.1-6
SIS 2023-12-07
11:20
Aichi Sakurayama Campus, Nagoya City University (Aichi, Online)
(Primary: On-site, Secondary: Online)
Development of a real-time non-photorealistic rendering system with a high-level synthesized pencil drawing style image conversion hardware
Honoka Tani, Akira Yamawaki (Kyutech) SIS2023-25
We developed non-photorealistic rendering (NPR) libraries optimized for high-level synthesis (HLS) technology that autom... [more] SIS2023-25
pp.7-12
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] 2023-11-16
14:10
Kumamoto Civic Auditorium Sears Home Yume Hall (Kumamoto, Online)
(Primary: On-site, Secondary: Online)
Hardware obfuscation method using Obfuscator-LLVM and Bambu
Mikiya Ogura, Shuichi Ichikawa (Toyohashi Univ. Tech.) VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57
Hardware obfuscation serves as a countermeasure against hardware reverse engineering. Yamada et al. employed the OLLVM s... [more] VLD2023-54 ICD2023-62 DC2023-61 RECONF2023-57
pp.125-130
MSS, CAS, SIP, VLD 2023-07-06
10:10
Hokkaido (Hokkaido, Online)
(Primary: On-site, Secondary: Online)
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
pp.10-15
HWS, VLD [detail] 2021-03-04
09:55
Online Online (Online) High-level synthesis of approximate circuits with two-level accuracies
Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama (Ritumeikan Univ.) VLD2020-80 HWS2020-55
This paper studies high-level synthesis (HLS) of approximate computing circuits with multiple accuracy levels. This work... [more] VLD2020-80 HWS2020-55
pp.67-72
VLD, IPSJ-SLDM 2016-05-11
14:30
Fukuoka Kitakyushu International Conference Center (Fukuoka) A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2016-4
In deep-submicron era, interconnection delays are not negligible even in high-level synthesis. RDR (Regular Distributed ... [more] VLD2016-4
pp.41-46
VLD 2016-03-01
15:10
Okinawa Okinawa Seinen Kaikan (Okinawa) FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis
Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-127
Recently, high-level synthesis techniques for FPGA designs (FPGA-HLS) are much focused on such as in image processing an... [more] VLD2015-127
pp.93-98
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-02
17:35
Nagasaki Nagasaki Kinro Fukushi Kaikan (Nagasaki) A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay and Clock Skew in FPGA Designs
Koichi Fujiwara, kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2015-54 DC2015-50
With recent process scaling in FPGAs, interconnection delays and clock skews have a large impact on the latency of a cir... [more] VLD2015-54 DC2015-50
pp.99-104
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2015-12-03
09:20
Nagasaki Nagasaki Kinro Fukushi Kaikan (Nagasaki) A Handshake-delay-aware Scheduling Algorithm in High-level Synthesis for Four-phase Dual-rail Asynchronous Systems
Kohta Itani, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2015-60 DC2015-56
This report is intended to discuss the scheduling problem in high-level synthesis~(HLS) for four-phase dual-rail asynchr... [more] VLD2015-60 DC2015-56
pp.147-152
 Results 1 - 13 of 13  /   
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