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Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 17 of 17  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2020-02-26
10:25
Tokyo   Defective Chip Prediction Modeling Using Convolutional Neural Networks
Ryunosuke Oka, Satoshi Ohtake (Oita Univ.), Kouichi Kumaki (Renesas) DC2019-87
In recent years, the cost of LSI testing which guarantees reliability has relatively increased due to the development of... [more] DC2019-87
pp.7-12
DC 2020-02-26
15:00
Tokyo   Improving Controllability of Signal Transitions in the High Switching Area of LSI
Jie Shi, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-94
Power consumption in LSI testing is larger than in functional mode. High power consumption causes excessive IR-drop and ... [more] DC2019-94
pp.49-54
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-06
14:55
Kumamoto Kumamoto-Kenminkouryukan Parea An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) VLD2017-36 DC2017-42
Today, semiconductor technologies have developed and advance the integration density of LSI circuits.
A technique which... [more]
VLD2017-36 DC2017-42
pp.55-60
DC 2017-02-21
12:00
Tokyo Kikai-Shinko-Kaikan Bldg. An Approach to Performance Improvement of Machine Learning Based Fail Chip Discrimination
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas System Design) DC2016-77
Today, advancements of semiconductor technology have progress to high integration of LSI circuits.
A technique which ke... [more]
DC2016-77
pp.17-22
DC 2016-06-20
16:15
Tokyo Kikai-Shinko-Kaikan Bldg. [Invited Talk] Internatoinal Conferecen Report: VTS2016
Kazumi Hatayama (Gunma Univ./Creatron Corp.) DC2016-16
This talk provide a report of VTS2016 (34th IEEE VLSI Test Symposium), which was held in Las Vegas, Nevada, USA, in Apri... [more] DC2016-16
pp.37-42
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2016-03-25
15:45
Nagasaki Fukue Bunka Hall/Rodou Fukushi Center A consideration on variation correction for fail prediction in LSI test
Ryo Ogawa (NAIST), Yoshiyuki Nakamura (Renesas Semiconductor Package & Test Solutions), Michiko Inoue (NAIST) CPSY2015-158 DC2015-112
Recently, a test cost reduction using data mining has been attracted. It is expected to reduce the cost by predicting fa... [more] CPSY2015-158 DC2015-112
pp.271-276
DC 2013-06-21
14:45
Tokyo Kikai-Shinko-Kaikan Bldg. A theretical discussion for testabilty of a degraded LSI in field
Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2013-12
Various electronic systems that consist of variety of LSIs require very high reliability in field. However, physical deg... [more] DC2013-12
pp.13-18
ICD, SDM 2012-08-02
14:40
Hokkaido Sapporo Center for Gender Equality, Sapporo, Hokkaido Intra/Inter Tier Substrate Noise Measurements in 3D ICs
Yasumasa Takagi, Yuuki Araga, Makoto Nagata (Kobe Univ.), Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Julien Ryckaert, Eric Beyne (IMEC) SDM2012-72 ICD2012-40
Substrate noise propagation among stacked dice is evaluated in a 3D test vehicle of 2 tier stacking. Each tier incorpora... [more] SDM2012-72 ICD2012-40
pp.49-54
ICD, ITE-IST 2011-07-22
10:50
Hiroshima Hiroshima Institute of Technology A Diagnosis Testbench of Analog IP Cores Against On-Chip Environmental Disturbances
Yuuki Araga, Takushi Hashida, Shinichiro Ueyama, Makoto Nagata (Kobe Univ.) ICD2011-29
Analog IP cores exhibit a multivariate response to dynamic variations of an operation environment,
that are typically r... [more]
ICD2011-29
pp.79-84
DC 2011-02-14
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. The development of the DDR3 memory module tester used on memory test processor
Takeshi Asakawa, Satoshi Matsuno (Tokai Univ.), Hidekazu Tsuchiya (Hitachi), Tatsuya Seki, Shinichi Kmazawa (Techinica) DC2010-59
The testing for the memory module is necessary to warrant the quality in the memory module manufacturer. However, there ... [more] DC2010-59
pp.1-6
DC 2010-02-15
13:20
Tokyo Kikai-Shinko-Kaikan Bldg. Reduction of execution times and areas for delay measurement by subtraction
Toru Tanabe, Hirohisa Minato, Kentaroh Katoh, Kazuteru Namba, Hideo Ito (Chiba Univ.) DC2009-71
Since VLSI is in nanoscase size, high density and high speed in recent years, small-delay defects which change propagati... [more] DC2009-71
pp.39-44
DC 2010-02-15
16:05
Tokyo Kikai-Shinko-Kaikan Bldg. Consideration of Open Faults Model Based on Digital Measurement of TEG Chip
Toshiyuki Tsutsumi (Meiji Univ.), Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) DC2009-77
Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. ... [more] DC2009-77
pp.75-80
ICD 2008-12-11
13:30
Tokyo Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan [Poster Presentation] Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring
Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.) ICD2008-108
Multi-channel waveform monitoring system for large-scale SoCs.
The system consists of probing front end circuits and a ... [more]
ICD2008-108
pp.39-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2008-11-17
14:15
Fukuoka Kitakyushu Science and Research Park Analysis of Open Fault using TEG Chip
Toshiyuki Tsutsumi, Yasuyuki Kariya, Koji Yamazaki (Meiji Univ), Masaki Hashizume, Hiroyuki Yotsuyanagi (Tokushima Univ), Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu (Ehime Univ) VLD2008-63 DC2008-31
The high integration of the semiconductor technology advances, and the fault detection and the failure diagnosis of LSI ... [more] VLD2008-63 DC2008-31
pp.19-24
ICD, ITE-IST 2008-10-24
09:20
Hokkaido Hokkaido University Evaluation of algorithms for waveform acquisition in on-chip multi-channel monitoring
Yuuki Araga, Takushi Hashida, Makoto Nagata (Kobe Univ.) ICD2008-80
Multi-channel waveform monitoring system for large-scale SoCs.
The system consists of probing front end circuits and a... [more]
ICD2008-80
pp.125-130
ICD, ITE-IST 2006-07-27
12:00
Shizuoka   A Signal Measurement System using On-Chip Multi-Channel Waveforme Monitor
Takushi Hashida, Koichiro Noguchi, Makoto Nagata (Kobe Univ.)
This paper describes measurement system consisted of a FPGA board and
on-chip multi-channel waveforme monitor circuits,... [more]
ICD2006-64
pp.23-28
RECONF 2005-05-12
09:30
Kyoto Kyoto University A Reconfigurable Embedded Decompressor for LSI Testing
Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
The problem of the increase in test data size for large-scale curcuits has developed.
In order to solve this problem, s... [more]
RECONF2005-1
pp.1-6
 Results 1 - 17 of 17  /   
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