Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, VLD |
2023-03-03 13:50 |
Okinawa |
(Primary: On-site, Secondary: Online) |
A Logic Locking Method based on Function Modification Circuit Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Rei Miura, Toshinori Hosokawa (Nihon Univ.) VLD2022-107 HWS2022-78 |
In recent years, with the increase of VLSI integration, semiconductor design companies to design a VLSI have tended to u... [more] |
VLD2022-107 HWS2022-78 pp.185-190 |
DC |
2022-03-01 13:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Primary: On-site, Secondary: Online) |
A Logic Locking Method based on SFLL-hd at Register Transfer Level Yohei Noguchi, Masayoshi Yoshimura (Kyoto Sangyo Univ.), Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.) DC2021-72 |
In recent years, with the increase of VLSI integration, LSI design companies utilize circuit design information, called ... [more] |
DC2021-72 pp.45-50 |
ED, THz |
2021-12-21 13:00 |
Miyagi |
(Primary: On-site, Secondary: Online) |
[Invited Talk]
Terahertz-wave control based on steric aspect of artificial structures Seigo Ohno (Tohoku Univ./RIKEN) ED2021-60 |
I will introduce two topics about artificial structures in which steric aspects play a significant role on terahertz wav... [more] |
ED2021-60 pp.58-61 |
DC |
2021-12-10 14:00 |
Kagawa |
(Primary: On-site, Secondary: Online) |
A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) DC2021-57 |
In recent years, to meet strict time-to-market constraints, it has become difficult for only one semiconductor design co... [more] |
DC2021-57 pp.13-18 |
SCE |
2021-08-06 14:35 |
Online |
Online |
Study on adiabatic quantum-flux-parametron datapaths with feedback loops adopting delay-line clocking Taiki Yamae (Yokohama Natl. Univ./JSPS Research Fellow), Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2021-4 |
Adiabatic quantum-flux-parametron (AQFP) is a superconductor logic family which can operate with low switching energy. S... [more] |
SCE2021-4 pp.14-18 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2021-03-26 12:00 |
Online |
Online |
A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94 |
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] |
CPSY2020-64 DC2020-94 pp.85-90 |
SCE |
2021-01-19 13:05 |
Online |
Online |
[Invited Talk]
Design of serializer/deserializer circuits for adiabatic quantum-flux-parametron circuits using delay-line clocking Yuki Hironaka, Taiki Yamae, Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2020-17 |
An adiabatic quantum-flux-parametron (AQFP) circuit is an extremely low-power Josephson logic family. A novel clocking s... [more] |
SCE2020-17 pp.1-6 |
SCE |
2021-01-19 13:55 |
Online |
Online |
Study and evaluation of adiabatic quantum-flux-parametron logic gates using delay-line clocking Taiki Yamae (Yokohama Natl. Univ./JSPS Research Fellow), Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2020-19 |
Adiabatic quantum-flux-parametron (AQFP) is a superconductor logic family, which can operate with low switching energy. ... [more] |
SCE2020-19 pp.13-18 |
PN |
2009-03-10 14:55 |
Okinawa |
Yonaguni Island |
Cycle Attack Free Logical Topology Design in OCDM Networks Yosuke Katsukawa, Shaowei Huang, Ken-ichi Kitayama (Osaka Univ.) PN2008-103 |
In OCDM networks there is a chance that cycle attack is caused by MAI(Multiaccess Interference) propagation and could di... [more] |
PN2008-103 pp.111-116 |
ICD, IPSJ-ARC |
2007-06-01 11:00 |
Kanagawa |
|
Design Techniques of Wave Pipelines Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.) ICD2007-28 |
In order to improve rather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning... [more] |
ICD2007-28 pp.67-72 |