Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ICD |
2024-04-12 13:50 |
Kanagawa |
(Primary: On-site, Secondary: Online) |
[Invited Lecture]
Development of a Bridge Chip for Scalable Performance and Capacity Storage Systems Shinichi Ikeda, Akira Iwata, Goichi Otomo, Tomoaki Suzuki, Hiroaki Iijima, Mikio Shiraishi, Shinya Kawakami, Masatomo Eimitsu, Yoshiki Matsuoka, Kiyohito Sato, Shigehiro Tsuchiya, Yoshinori Shigeta, Takuma Aoyama (Kioxia) ICD2024-14 |
We describe a Bridge Chip that enables a high-speed, high-capacity storage system. The proposed Bridge Chip employs a fu... [more] |
ICD2024-14 p.43 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 09:55 |
Kumamoto |
(Primary: On-site, Secondary: Online) |
Design of Digital Phase-Locked Loop Circuit based on 3rd-Order MASH ΔΣ FDC for Low In-Band Phase Noise Ryoga Iwashita, Zule Xu, Masaru Osada, Ryoya Shibata, Yo Kumano, Tetsuya Iizuka (UTokyo) VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 |
$DeltaSigma$ frequency-to-digital converter based phase locked loops (FDC-PLLs) can reduce its quantization noise at low... [more] |
VLD2022-43 ICD2022-60 DC2022-59 RECONF2022-66 pp.138-143 |
OPE, OCS, LQE |
2022-10-20 15:10 |
Ehime |
(Primary: On-site, Secondary: Online) |
Signal Phase Recovery Using Digital Signal Processing in Optical Wireless Communication Systems Ryoma Murakami, Shiro Ryu (Meiji Univ.) OCS2022-21 OPE2022-67 LQE2022-30 |
Research and development of optical wireless communication systems has been active. Optical receivers usually use a phas... [more] |
OCS2022-21 OPE2022-67 LQE2022-30 pp.22-27 |
ICD, SDM, ITE-IST [detail] |
2022-08-08 16:35 |
Online |
|
[Invited Talk]
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur Zule Xu, Masaru Osada, Tetsuya Iizuka (UTokyo) SDM2022-43 ICD2022-11 |
We present a type-II fractional-N hybrid switched-capacitor sampling PLL, using a capacitive digital-to-analog converter... [more] |
SDM2022-43 ICD2022-11 pp.41-44 |
CAS, CS |
2022-03-03 12:45 |
Online |
Online |
[Memorial Lecture]
Integration Techniques of Phase Locked Loops on high-speed and high- precision for wireline and wireless applications Masaru Kokubo (Hitachi) CAS2021-78 CS2021-80 |
The configurations of the PLLs for modulation are described. This paper summarizes the technical points in the integrate... [more] |
CAS2021-78 CS2021-80 pp.25-30 |
RISING (3rd) |
2021-11-17 11:00 |
Tokyo |
(Primary: On-site, Secondary: Online) |
Study on Synchronization Strategy for Maximizing Received Power in Distributed Microwave Wireless Power Transfer Systems Kentaro Matsuura, Koeru Shin, Daisuke Kobuchi, Yoshiaki Narusue, Hiroyuki Morikawa (UTokyo) |
We propose a design strategy of the synchronization period to maximize the time-averaged received power in the distribut... [more] |
|
RCS, AP, UWT (Joint) |
2020-11-25 13:55 |
Online |
Online |
Phase Noise Compensation Using LMS Algorithm and PLL for FDE in SISO Channels Kana Aono, Mamoru Sawahashi (Tokyo City Univ.) RCS2020-116 |
This paper presents the bit error rate (BER) performance of phase noise compensation (PNC) with least mean square (LMS) ... [more] |
RCS2020-116 pp.36-41 |
MW, ICD |
2019-03-15 11:00 |
Okinawa |
|
An Energy-Saving Digital-to-Time Converter for Ultra-Low-Power Digital PLLs Hongye Huang, Hanli Liu, Zheng Sun, Teruki Someya, Atsushi Shirane, Kenichi Okada (Tokyo Tech) MW2018-172 ICD2018-116 |
A digital-to-time converter (DTC) could be a critical part in a digital phase-locked loop (PLL). Comparing to other DTC ... [more] |
MW2018-172 ICD2018-116 pp.87-91 |
ICD, CPSY, CAS |
2018-12-23 09:30 |
Okinawa |
|
[Poster Presentation]
Evaluation of performance of 5GHz PLL with high-frequency injection pulses Yuuki Kojima, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-97 ICD2018-81 CPSY2018-63 |
Recent years, The high-frequency and the low-jitter clock generation is required due to speeding up of the communication... [more] |
CAS2018-97 ICD2018-81 CPSY2018-63 pp.81-82 |
ICD, CPSY, CAS |
2018-12-23 09:30 |
Okinawa |
|
[Poster Presentation]
Evaluation of jitter performance with external- and self-injection in PLL circuit Tatsuya Okafuji, Kazuki Miyao, Takao Kihara, Tsutomu Yoshimura (OIT) CAS2018-100 ICD2018-84 CPSY2018-66 |
In recent years, high-speed clock with high precision is required as communication speed increases. We have confirmed th... [more] |
CAS2018-100 ICD2018-84 CPSY2018-66 pp.91-93 |
MW |
2018-11-15 13:30 |
Nagasaki |
Fukue Cultural Hall |
Phase Control Method for Subsampling PLL by Varying Phase and Frequency of Clock Signal of S/H Circuit Osamu Wada, Hiroyuki Mizutani, Kenichi Tajima (Mitsubishi Electric Corp.) MW2018-97 |
A phase control method of PLL that generates a LO signal was reported as controlling a phase difference between transmi... [more] |
MW2018-97 pp.31-34 |
ICD, MW |
2018-03-02 13:50 |
Shiga |
The University of Shiga Prefecture |
An identification method of interference signals by phase shift of chirp signal in FMCW radar using PLL Hideyuki Nakamizo, Kenichi Tajima (Mitsubishi Electric Corporation) MW2017-195 ICD2017-119 |
It is difficult for a receiver of FMCW radar to distinguish a desired reflected FMCW signal from undesired interference ... [more] |
MW2017-195 ICD2017-119 pp.103-107 |
ICD, CPSY, CAS |
2017-12-15 09:30 |
Okinawa |
Art Hotel Ishigakijima |
A 28GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G New Radio Hanli Liu, Teerachot Siriburaron, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Tech.) CAS2017-101 ICD2017-89 CPSY2017-98 |
The increasing demand for larger data capacity drives researchers finding new spectrum beyond 4G, i.e., 28GHz frequency ... [more] |
CAS2017-101 ICD2017-89 CPSY2017-98 pp.147-150 |
SITE, EMM, ISEC, ICSS, IPSJ-CSEC, IPSJ-SPT [detail] |
2017-07-14 16:10 |
Tokyo |
|
Report of solving SVP's by using DeepLLL Junpei Yamaguchi, Masaya Yasuda (Kyushu Univ.) ISEC2017-23 SITE2017-15 ICSS2017-22 EMM2017-26 |
Lattice-based cryptography is based on the computational herdbess of lattice problems such as Shortest vector problem (S... [more] |
ISEC2017-23 SITE2017-15 ICSS2017-22 EMM2017-26 pp.115-122 |
MW, ICD |
2017-03-02 14:25 |
Okayama |
Okayama Prefectural Univ. |
Linearity Improvement Method of Fast-Chirp Signal for PLL by Using Frequency Detector and Division Ratio Modification Osamu Wada, Hiroyuki Mizutani, Hideyuki Nakamizo, Kenichi Tajima (Mitsubishi Electric corp.) MW2016-197 ICD2016-127 |
A fast-chirp signal generated by a PLL is distorted by its transient characteristic and it has overshooting around turn-... [more] |
MW2016-197 ICD2016-127 pp.51-54 |
MW, ICD |
2017-03-03 10:25 |
Okayama |
Okayama Prefectural Univ. |
Study of Wide band width LC type Injection-locked Frequency Divider with Capacitor Array Yoshitake Nishino, Nobuyuki Itoh, Takayuki Morishita, Kiyotaka Komoku (Okayama Prefectural Univ.) MW2016-206 ICD2016-136 |
An injection-locked frequency divider(ILFD)with capacitor array is studied to obtain a wide locking range and high input... [more] |
MW2016-206 ICD2016-136 pp.101-106 |
RCS, SR, SRW (Joint) |
2017-03-03 17:25 |
Tokyo |
Tokyo Institute of Technology |
BER Performance of Pilot Symbol Assisted and PLL Phase Noise Estimation Methods for High-Order Circular QAM Bin Zheng, Lianjun Deng, Mamoru Sawahashi (Tokyo City Univ.), Norifumi Kamiya (NEC) RCS2016-336 |
This paper presents bit error rate (BER) performance of Circular Quadrature Amplitude Modulation (QAM) constellation whi... [more] |
RCS2016-336 pp.265-270 |
OFT, OCS, IEE-CMN, ITE-BCT [detail] |
2016-11-10 16:25 |
Nagasaki |
Nagasaki Shoko Kaigi Sho |
Automatic pull-in operation in heterodyne phase-lock and homodyne detection of QPSK signals by microcomputer-assisted loop filter Yudai Hisata, Akira Mizutori, Masafumi Koga (Oita Univ.) OCS2016-58 |
This paper demonstrates signal light carrier automatic pull-in and phase-lock operation to optical frequency comb refere... [more] |
OCS2016-58 pp.9-12 |
MW |
2016-05-20 11:10 |
Kyoto |
Kyoto Univ. |
A Fast Chirp Generation PLL-IC using Polarity Switching Loop Filter Koji Tsutsumi, Eiji Taniguchi (Mitsubishi Electric) MW2016-19 |
A PLL (Phase Locked Loop) is used to generate frequency chirp signal for FMCW radars. The chirp generator using PLL has ... [more] |
MW2016-19 pp.47-50 |
MW |
2016-01-14 14:15 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
A Frequency Synchronization Scheme for Time Varying Doppler-shift Compensation using the Direct Return Signal Keisuke Nakamura, Osamu Wada, Kenichi Tajima, Morishige Hieda (Mitsubishi Electric) MW2015-161 |
In this paper, a frequency synchronization scheme between platforms for a bistatic SAR is described. The proposed scheme... [more] |
MW2015-161 pp.13-16 |