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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 13:55 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Design and implementation of a RISC-V soft processor adopting five-stage pipelining Hiromu Miyazaki, Takuto Kanamori, Md Ashraful Islam, Kenji Kise (Tokyo Tech)  VLD2019-73 CPSY2019-71 RECONF2019-63 |
In this paper, we propose a RISC-V soft processor adopting five-stage pipelining optimized for FPGAs that support RV32I,... [more] | VLD2019-73 CPSY2019-71 RECONF2019-63 pp.123-128 |
| IN, NS (Joint) |
2019-03-05 09:00 |
Okinawa | Okinawa Convention Center | Multipoint high-speed transfer experiment using big data of fusion experiment device LHD Kenjiro Yamanaka (Sokendai/NII), Hideya Nakanishi (NIFS), Takahisa Ozeki, Shinsuke Tokunaga, Yasutomo Ishii (QST), Shunji Abe, Shigeo Urushidani (Sokendai/NII), Takashi Yamamoto, Masahiko Emoto (NIFS) NS2018-233 |
In the advanced science and technology field, we often make huge experiment / observation equipment with international c... [more] | NS2018-233 pp.237-242 |
| NS, IN (Joint) |
2018-03-01 10:50 |
Miyazaki | Phoenix Seagaia Resort | Remote replication for LHD's large data
-- 4 Gbps data transfer of 145 TB data using MMCFTP and piplelined replication -- Kenjiro Yamanaka (SOKENDAI/NII), Hideya Nakanishi (NIFS), Takahisa Ozeki (QST), Shunji ABE, Shigeo Urushidani (SOKENDAI/NII), Takashi Yamamoto, Masahiko Emoto, Noriyoshi Nakajima (NIFS) NS2017-180 |
Large volumes of data shared internationally in advanced research projects are often composed of many small files. Trans... [more] | NS2017-180 pp.73-78 |
| SANE | 2014-10-24 11:40 |
Overseas | Ramada Plaza Melaka, Malacca, Malaysia | The Design and Development of Synthetic Aperture Radar (SAR) Imaging Field Programmable Gate Array (FPGA)-based Processor Yung Chong Lee, Voon Chet Koo, Yee Kit Chan (Multimedia Univ.) SANE2014-100 |
Synthetic Aperture Radar (SAR) is an all-weather microwave remote sensing system which is invented from the concept of c... [more] | SANE2014-100 pp.201-206 |
| RECONF | 2014-09-19 10:10 |
Hiroshima | Building a Mixed Software Hardware Pipeline on CPU-FPGA Platforms Takaaki Miyajima (Keio Univ.), David Thomas (ICL), Hideharu Amano (Keio Univ.) RECONF2014-27 |
This new toolchain for accelerating application on CPU-FPGA platforms, called Courier-FPGA, extracts runtime information... [more] | RECONF2014-27 pp.57-62 |
|
| VLD, IPSJ-SLDM | 2014-05-29 15:15 |
Fukuoka | Kitakyushu International Conference Center | An Automatic Nested Loop Pipelining Method and Its Evaluation Yusuke Nakatsuji, Masahiro Nambu, Takashi Kambe (Kinki Univ.) VLD2014-9 |
Nested loop pipelining with keeping data dependency is a key transformation in high-level synthesis tools as it helps ma... [more] | VLD2014-9 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2013-11-29 10:25 |
Kagoshima | Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.) VLD2013-95 DC2013-61 |
In the loop pipelining of high-level synthesis, the reduction of initiation intervals (IIs) is very important. Existing ... [more] | VLD2013-95 DC2013-61 pp.245-249 |
|
| RECONF | 2013-09-19 13:25 |
Ishikawa | Japan Advanced Institute of Science and Technology | A study of pipeline execution on PEACH2 Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Tsukuba Univ.), David Thomas (Imperial College), Hideharu Amano (Keio Univ.) RECONF2013-33 |
PEACH2 (PCI-Express Adaptive Communication Hub 2) is a inter/intra node communication enhance- ment system for HA-PACS, ... [more] | RECONF2013-33 pp.79-84 |
| VLD, IPSJ-SLDM | 2013-05-16 15:00 |
Fukuoka | Kitakyushu International Conference Center | Data Dependence Relaxation Techniques for Reducing Iteration Intervals in Pipelined Loops Shingo Kusakabe, Kenshu Seto (Tokyo City Univ.) VLD2013-7 |
In the loop pipelining of high-level synthesis, the sum of the delays in the cycles of the data dependence graph is a ma... [more] | VLD2013-7 pp.55-60 |
| VLD | 2012-03-06 14:00 |
Oita | B-con Plaza | A loop pipeling method for irregular nested loops Takashi Takenaka, Kazutoshi Wakabayashi (NEC), Yuka Nakagoshi (NIS) VLD2011-126 |
This paper presents a behavioral synthesis method for pipelining irregular nested loops. An irregular nested loop is ... [more] |
VLD2011-126 pp.37-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:50 |
Miyazaki | NewWelCity Miyazaki | Automatic Loop Fusion for High Level Synthesis using Outer Loop Shifting Yuta Kato, Kenshu Seto, Takuya Maruizumi (TCU) VLD2011-69 DC2011-45 |
When designing hardware with high-level synthesis tools, it is often necessary to manually perform loop restructuring op... [more] | VLD2011-69 DC2011-45 pp.103-108 |
| VLD | 2011-03-03 13:45 |
Okinawa | Okinawaken-Danjo-Kyodo-Sankaku Center | A Circuit Synthesis for High Speed Memory Access in System LSI Kazuya Kishida, Takashi Kambe (Kinki Univ.) VLD2010-130 |
In system LSI, large-scale data is accessed from off-chip memory in many cases, and the architecture design of the memor... [more] | VLD2010-130 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2009-12-02 11:00 |
Kochi | Kochi City Culture-Plaza | A WiMAX Turbo Decoder with Tailbiting BIP Architecture Hiroaki Arai, Naoto Miyamoto, Koji Kotani (Tohoku Univ.), Hisanori Fujisawa (Fujitsu Laboratories Ltd.), Takashi Ito (Tohoku Univ.) CPM2009-136 ICD2009-65 |
In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy e... [more] | CPM2009-136 ICD2009-65 pp.13-18 |
| VLD, ICD | 2008-03-07 15:45 |
Okinawa | TiRuRu | A Circuit Design of Reed-Solomon Decoder using Dynamically Reconfigurable Processor Atsurou Yoshida, Yuji Higashi, Wataru Miyazaki, Teruhito Tanaka, Takashi Kambe (Kinki University) VLD2007-167 ICD2007-190 |
Reed-Solomon Decoder can correct continues error and it has been a popular technology for various devices such as commu... [more] |
VLD2007-167 ICD2007-190 pp.65-68 |
| VLD, IPSJ-SLDM | 2007-05-10 15:20 |
Kyoto | Kyodai Kaikan | An Architecture Design and its Evaluation for Speech Recognition System Joh Hashimato, Makoto Saitsuji, Takashi Kambe (Kinki Univ.) VLD2007-5 |
Speech recognition is becoming a popular technology for the implementation of human interfaces. However, conventional ap... [more] | VLD2007-5 pp.25-30 |
| RECONF, CPSY, VLD, IPSJ-SLDM | 2006-01-18 15:20 |
Kanagawa | A Performance Improvement Strategy for Numerical Integration on an FPGA-Based Biochemical Simulator ReCSiP Yuri Nishikawa, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Toshinori Kojima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) |
Computational simulation is a highly effective solution for cellular analyses in recent bioinformatics. As the scale of... [more] | VLD2005-106 CPSY2005-62 RECONF2005-95 pp.53-58 |
|
| SIP, ICD, IE, IPSJ-SLDM | 2005-10-21 10:50 |
Miyagi | Ichinobo, Sakunami-Spa | Compaction of Arithmetic Unit with Bit-Level-Parallelism Jubee Tada (Yamagata Univ.), Ryusuke Egawa (Tohoku Univ.), Gensuke Goto (Yamagata Univ.), Tadao Nakamura (Tohoku Univ.) |
Aiming at reducing power consumption of VLSIs, we propose a fast and compact arithmetic unit. The arithmetic unit reduc... [more] | SIP2005-120 ICD2005-139 IE2005-84 pp.31-35 |
| CAS, SIP, VLD | 2005-06-28 14:50 |
Miyagi | Tohoku University | Complementary Ferroelectric Capacitor Logic and its Application to Fully Parallel Arithmetic VLSI Shoun Matsunaga, Takahiro Hanyu (Tohoku Univ.) |
In this paper, we propose a Complementary Ferroelectric Capacitor Logic-in-Memory circuit that makes it possible easily ... [more] | CAS2005-25 VLD2005-36 SIP2005-49 pp.61-65 |
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