IEICE Technical Committee Submission System
Conference Schedule
Online Proceedings
[Sign in]
Tech. Rep. Archives
    [Japanese] / [English] 
( Committee/Place/Topics  ) --Press->
 
( Paper Keywords:  /  Column:Title Auth. Affi. Abst. Keyword ) --Press->

All Technical Committee Conferences  (Searched in: All Years)

Search Results: Conference Papers
 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 68  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
RECONF 2023-08-04
14:55
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning
Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo) RECONF2023-15
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] RECONF2023-15
pp.7-12
RECONF 2022-06-07
13:25
Ibaraki CCS, Univ. of Tsukuba
(Primary: On-site, Secondary: Online)

Shoin Maeda, Hiroshi Nakamura, Hideki Takase (UT) RECONF2022-2
To expand the application area of model predictive control (MPC), a control system design framework that guarantees the ... [more] RECONF2022-2
pp.7-12
RCS, SR, SRW
(Joint)
2019-03-08
11:20
Kanagawa YRP Multi-Band RF Hardware Techniques for 5G Mobile Communication Systems
Yasushi Yamao, Kazuhiko Honjo, Ryo Ishikawa, Yoichiro Takayama, Akira Saito (UEC) RCS2018-325
R & D of 5G mobile communication systems are intensively conducted as joint projects by industries, academia and the gov... [more] RCS2018-325
pp.219-224
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2018-12-06
09:00
Hiroshima Satellite Campus Hiroshima Resources Utilization of Fine-grained Overlay Architecture
Theingi Myint (Kumamoto), Qian Zhao (Kyutech), Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto) RECONF2018-37
This paper focuses on utilization of hardware resources for fine-grained overlay architecture. Overlay architectures inc... [more] RECONF2018-37
pp.15-20
RECONF 2017-09-26
11:00
Tokyo DWANGO Co., Ltd. [Invited Talk] Increasing Productivity Using Xilinx Development Tools
Louie Valena (Xilinx) RECONF2017-33
Xilinx offers several tools to ease the development of complex hardware-software systems. Tools such as Vivado HLS, SDSo... [more] RECONF2017-33
pp.63-68
NS, IN
(Joint)
2017-03-03
14:50
Okinawa OKINAWA ZANPAMISAKI ROYAL HOTEL Low-Power Edge Computing over Virtual Programmable Photonic Edge
Jun Matsumoto, Takehiro Sato, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.), Kazuo Sugai, Takayuki Muranaka (ALAXALA Networks) NS2016-224
The concept of Programmable Photonic Edge (PPE) has been proposed which uses reconfigurable communication processers com... [more] NS2016-224
pp.383-388
ICD, IE, VLD, IPSJ-SLDM [detail] 2015-10-27
09:00
Miyagi   [Tutorial Invited Lecture] Prospects of Intelligent Systems for Real-World Applications and Their VLSI Computing Platform
Michitaka Kameyama (Tohoku Univ.) VLD2015-33 ICD2015-46 IE2015-68
A computing platform for real-world intelligent systems is desired to contribute to low-cost implementation as well as h... [more] VLD2015-33 ICD2015-46 IE2015-68
pp.37-42
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2014-11-28
11:10
Oita B-ConPlaza [Fellow Memorial Lecture] Looking Back over My Researches on Flexible Hardware -- Reconfigurable Systems and FPGAs --
Toshinori Sueyoshi (Kumamoto Univ.) CPSY2014-83
As IEICE Fellow commemorative lecture, I look back over my researches of more than 30 years on Flexible Hardware such as... [more] CPSY2014-83
pp.63-68
RECONF 2014-06-12
09:00
Miyagi Katahira Sakura Hall A Dynamic Reconfigurable Mixed Analog-Digital Filter -- Applied to an Acoustic Diagnostic --
Hiroki Nakahara, Hideki Yoshida (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Renji Mikami (Mikami Consul.) RECONF2014-2
A cochlear filter bank for an audio band is used for an acoustic diagnostic,
which detects broken points of a wall.
H... [more]
RECONF2014-2
pp.5-10
IPSJ-SLDM, CPSY, RECONF, VLD [detail] 2014-01-29
10:25
Kanagawa Hiyoshi Campus, Keio University Implementation of MuCCRA-4: Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) VLD2013-122 CPSY2013-93 RECONF2013-76
Although Dynamically Reconfigurable Processor Arrays (DRPAs) are advantageous for embedded devices because of their high... [more] VLD2013-122 CPSY2013-93 RECONF2013-76
pp.119-124
IE, ICD, VLD, IPSJ-SLDM [detail] 2013-10-08
10:35
Aomori   New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic
Xu Bai, Michitaka Kameyama (Tohoku Univ.) VLD2013-57 ICD2013-81 IE2013-57
This article presents a fine-grain reconfigurable VLSI based on multiple-valued X-net data transfer scheme. Two binary d... [more] VLD2013-57 ICD2013-81 IE2013-57
pp.59-64
RECONF 2013-09-18
15:30
Ishikawa Japan Advanced Institute of Science and Technology An Implementation of High Performance Stream Processing on a Reconfigurable Hardware
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) RECONF2013-21
Stream processing is one of the applications that reconfigurable hardware can be highly effective. In this paper, we giv... [more] RECONF2013-21
pp.7-12
DC 2013-06-21
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. An Online Interconnect Test of SoC with Boundary Scan Shift and Embedded Reconfigurable Core
Kentaroh Katoh (TNCT) DC2013-14
This paper presents an online Interconnect test of SoC with Boundary Scan Shift and embedded reconfigurable core. The pr... [more] DC2013-14
pp.25-29
IN 2013-06-20
14:25
Fukui University of Fukui, Bunkyo Campus, Memorial Academy Hall Writing Window Join Processor in C
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Tetsuya Asai, Masato Motomura (Hokkaido Univ.) IN2013-26
In the past, there has always been a wide gap between the skills for designing software and hardware. Now that reconfigu... [more] IN2013-26
pp.7-12
RECONF 2013-05-20
16:25
Kochi Kochi Prefectural Culture Hall Speed-up of Dynamically Reconfigurable Processor Array
Toru Katagiri, Hideharu Amano (Keio Univ.) RECONF2013-5
In order to achieve a high performance on the Dynamically Reconfigurable Processor Array (DRPA), it is common to increas... [more] RECONF2013-5
pp.25-30
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2013-03-14
09:10
Nagasaki   Guarantee of finising of calculate for a low power accelerator CMA
Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuaki Ozaki, Hideharu Amano (Keio Univ.) CPSY2012-86 DC2012-92
Cool Mega-Array (CMA) is a novel high performance but low power
reconfigurable accelerator consisting of a large PE (Pr... [more]
CPSY2012-86 DC2012-92
pp.205-210
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-27
17:00
Fukuoka Centennial Hall Kyushu University School of Medicine [Keynote Address] Dynamically Reconfigurable Processor (DRP) Technology: Current Status and Future Prospects
Masato Motomura (Hokkaido Univ.), Koichiro Furuta, Toru Awashima, Yasunari Shida (Renesas Electronics) VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49
DRP features two dimensional array of tiny processors and memories, onto which applications are compiled and mapped as a... [more] VLD2012-87 CPM2012-117 ICD2012-81 CPSY2012-55 DC2012-53 RECONF2012-49
p.163(VLD), p.29(CPM), p.29(ICD), p.45(CPSY), p.163(DC), p.15(RECONF)
RECONF 2012-05-29
16:45
Okinawa Tiruru (Naha Okinawa, Japan) Implementation and evaluation of the AES/ADPCM on STP and FPGA with Behavioral Synthesis
Yukihito Ishida, Seiya Shibata, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ) RECONF2012-14
Reconfigurable techniques are attracting attention as an alternative to dedicated hardware of SoC.
We have evaluated FP... [more]
RECONF2012-14
pp.77-82
US 2011-09-26
15:15
Miyagi Tohoku Univ. System flexibility of medical ultrasound equipment
Takaya Uno (Hitachi Aloka Medical,Ltd.) US2011-49
Commercial Medical Ultrasound Equipment is combined hardware and software very complexly. Thus, many researchers cannot ... [more] US2011-49
pp.17-21
RECONF 2011-09-27
11:25
Aichi Nagoya Univ. A proposal of pattern matching techniques using dynamically reconfigurable hardware
Masato Nogami, Nobuya Watanabe, Akira Nagoya (Okayama Univ.) RECONF2011-37
The pattern matching of the strings using hardware has the problem that increases circuit size when the number of patter... [more] RECONF2011-37
pp.87-92
 Results 1 - 20 of 68  /  [Next]  
Choose a download format for default settings. [NEW !!]
Text format pLaTeX format CSV format BibTeX format
Copyright and reproduction : All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan