Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
NLP, CAS |
2023-10-06 09:20 |
Gifu |
Work plaza Gifu |
A Simulation Comparison of Chaotic Circuits Under Different Memristor SPICE Models Yasuhiro Takahashi (Gifu Univ.) CAS2023-30 NLP2023-29 |
With the advent of memristor using titanium oxide thin films, that is, HP memristor, various SPICE models of HP memristo... [more] |
CAS2023-30 NLP2023-29 pp.1-4 |
HWS |
2023-04-14 13:20 |
Oita |
(Primary: On-site, Secondary: Online) |
Exploration of hardware Trojan detection through power supply current simulation Takafumi Oki, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2023-1 |
The recent development of information and communication technology has increased the demand for integrated circuit (IC) ... [more] |
HWS2023-1 pp.1-5 |
SDM |
2022-11-11 17:15 |
Online |
Online |
Measurement and Modeling of Cycle-to-Cycle Variability in ReRAM Devices Shoma Yoshimoto, Masaki Takemori, Yoshinari Kamakura (OIT) SDM2022-78 |
Cycle-to-cycle (C2C) variability in ReRAM devices is investigated experimentally. The measured data are fitted to the SP... [more] |
SDM2022-78 pp.68-72 |
EE, IEE-SPC (Joint) |
2022-03-10 14:55 |
Online |
Online |
Analytical Investigation of Phase-Shift Full Bridge Converter with Reduced Surge Voltage Kunpei Yoshikawa, Kenichi Suzuki (Shindengen), Kimihiro Nishijima (Sojo Univ.) EE2021-55 |
Phase-shift full bridge converter is widely used for automotive dc-dc converter design due to its wide input voltage ran... [more] |
EE2021-55 pp.18-22 |
SDM |
2021-11-12 17:10 |
Online |
Online |
Inference of MOSFET Characteristics and Parameters with Machine Learning Kohei Akazawa, Yuigo Nakanishi, Yuhei Suzuki, Yoshinari Kamakura (Osaka Inst. Technol.) SDM2021-67 |
A machine learning method to extract SPICE model parameters is discussed. The data set is obtained from SPICE simulatio... [more] |
SDM2021-67 pp.77-80 |
HWS, ICD [detail] |
2021-10-19 11:15 |
Online |
Online |
High-Efficiency simulation method for evaluating power noise and side-channel leakage in crypto modules Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2021-44 ICD2021-18 |
In semiconductor integrated circuits of cryptographic modules, the side-channel leakage from power supply noise is criti... [more] |
HWS2021-44 ICD2021-18 pp.19-22 |
NS, IN (Joint) |
2020-03-06 15:30 |
Okinawa |
Royal Hotel Okinawa Zanpa-Misaki (Cancelled but technical report was issued) |
Analysis of Relationship between Rectifier Smoothing Circuit and Occurrence of Communications Forbidden Time of PLC System
-- Part 2: Simulation Analysis using SPICE Model -- Hiroshi Gotoh, Wataru Abe, Kenji Kita (Toyo Univ.), Hiroyasu Ishikawa (Nihon Univ.), Hideyuki Shinonaga (Toyo Univ.) NS2019-262 |
PLC(Power Line Communications) is a communication technology using power line as a transmission medium. In the previous ... [more] |
NS2019-262 pp.485-488 |
MBE, NC |
2019-10-12 11:45 |
Miyagi |
|
LSI Implementation and Its Evaluation of an Izhikevich Model Neuron Analog MOS Circuit Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Shigeo Sato, Yoshihiko Horio (Tohoku Univ.) MBE2019-44 NC2019-35 |
The Izhikevich neuron model, which can reproduce various spike activities with a small amount of calculation, is indispe... [more] |
MBE2019-44 NC2019-35 pp.69-73 |
NC, MBE (Joint) |
2019-03-04 16:10 |
Tokyo |
University of Electro Communications |
Proposal of an Izhikevich Model Neuron MOS Circuit Yuki Tamura, Satoshi Moriya, Tatsuki Kato, Masao Sakuraba, Yoshihiko Horio, Shigeo Sato (Tohoku Univ.) NC2018-60 |
The Izhikevich neuron model, which can reproduce various spike activities with a small amount of calculation, is indispe... [more] |
NC2018-60 p.93 |
EMD, R |
2019-02-15 14:55 |
Osaka |
|
[Invited Talk]
SPICE based circuit performance degradation simulation with MOSFET aging models Koji Tanaka, Shinichiro Amemiya, Hitoshi Okamura, Masanori Shimasue (MoDeCH) R2018-56 EMD2018-57 |
Now, semiconductor products are used in many high reliability products such as vehicle parts and medical equipment. Natu... [more] |
R2018-56 EMD2018-57 pp.25-30 |
NC, MBE (Joint) |
2018-10-19 14:00 |
Miyagi |
Tohoku Univ. |
A study on an Izhikevich Model Neuron MOS Circuit Yuki Tamura, Satoshi Moriya, Masao Sakuraba, Shigeo Sato (Tohoku Univ.) NC2018-13 |
The Izhikevich neuron, which can reproduce various spike activities with a small amount of calculation, is indispensable... [more] |
NC2018-13 pp.1-5 |
WPT, EE (Joint) |
2018-10-04 10:50 |
Kyoto |
Kyoto Univ. Uji Campus |
Consideration of CEMS Model Combining SPICE and MATLAB Misa Ito, Yuta Oshima, Rei Kawai (NIT, Toyama), Noboru Ishihara (Tokyo Tech), Iwao Mizumoto, Hiroshi Oguma (NIT, Toyama) EE2018-23 |
We develop the simulation models of photovoltaic (PV) power generation system, storage battery system, and electric appl... [more] |
EE2018-23 pp.29-34 |
ICD, CPSY |
2016-12-16 09:40 |
Tokyo |
Tokyo Institute of Technology |
Automatic Design of Bias Circuit Based on the Results of Characterized MOSFET Kento Suzuki, Nobukazu Takai, Yoshiki Sugawara, Kazuto Okochi, Satoshi Yoshizawa, Tsukasa Ishii, Saki Shinoda, Masafumi Fukuda (Gunma Univ.) ICD2016-91 CPSY2016-97 |
It is difficult to design optimal analog circuit in a short time in terms of designing flexibility. In an analog circuit... [more] |
ICD2016-91 CPSY2016-97 pp.119-122 |
EE, CPM |
2015-02-27 13:25 |
Tokyo |
NTT Musashino R&D Center |
Home Energy Management System Simulation with SPICE Noboru Ishihara, Tomonobu Itagaki, Takashi Suganuma, Toyonari Shimakage (TIT), Taku Ishibashi, Norikazu Takeuchi (NTT Facilities), Nobuhiko Yamashita (NTT), Kenji Yokoyama, Kazuya Masu (TIT) EE2014-46 CPM2014-160 |
The home energy management systems (HEMS) using natural energy such as sunlight are spreading as one way to build a low... [more] |
EE2014-46 CPM2014-160 pp.31-36 |
NLP |
2014-07-21 16:25 |
Hokkaido |
Hakodate City Central Library |
DC operating point analysis of nonlinear circuits using the variable-gain Newton fixed-point homotopy method Keiichi Moriyama, Kiyotaka Yamamura (Chuo Univ.) NLP2014-38 |
In the field of circuit simulation, homotopy methods have been studied by many researchers in order to overcome the non-... [more] |
NLP2014-38 pp.37-42 |
VLD, IPSJ-SLDM |
2014-05-29 13:25 |
Fukuoka |
Kitakyushu International Conference Center |
Error Tolerance of Dual Pipeline Self Synchronous Circuits Sai Denki, Makoto Ikeda (Univ. of Tokyo) VLD2014-7 |
Soft errors caused by collision of neutrons in cosmic rays and atoms in LSIs in electronic equipment are believed to be ... [more] |
VLD2014-7 pp.33-38 |
EE, CPM |
2014-02-27 15:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
On switching characteristics and equivalent circuit of SiC-BGSIT device Yukitaka I, Akihumi Ogawa, Tetsuro Tanaka (Kagoshima Univ.) EE2013-56 CPM2013-157 |
The objective of this report is to experimentally investigate the occurrence conditions of false operation caused by the... [more] |
EE2013-56 CPM2013-157 pp.43-48 |
CAS, NLP |
2011-10-21 15:30 |
Shizuoka |
Shizuoka Univ. |
The 1/f Noise Generation in Charge-Pump Phase-Locked Loops
-- Simulation Study by LT-SPICE -- Kyosuke Kato, Yuhei Chiba, Isao Imai, Tetsuro Endo (Meiji Univ.) CAS2011-58 NLP2011-85 |
In this report we perform simulation study of a charge-pump phase-locked loop (CP-PLL) with frequency-modulated input si... [more] |
CAS2011-58 NLP2011-85 pp.147-152 |
ICD |
2010-12-16 15:10 |
Tokyo |
RCAST, Univ. of Tokyo |
[Poster Presentation]
MOS SPICE Model Evaluation Based on gm/Id Lookup Table Methodology Kenji Inazu, Toru Kashimura, Takayuki Konishi (Tohoku Univ.), Takana Kaho (NTT), Shoichi Masui (Tohoku Univ.) ICD2010-113 |
We propose a SPICE model parameter evaluation method based on gm/ID lookup table design methodology for analog/mixed-sig... [more] |
ICD2010-113 pp.89-94 |
DC, CPSY |
2009-04-21 16:10 |
Tokyo |
Akihabara Satellite Campus, Tokyo Metropolitan Univ. |
Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design. Daisuke Kozuwa, Masayoshi Yoshimura, Yusuke Matsunaga (Kyusyu Univ.) CPSY2009-8 DC2009-8 |
The charge deposition that results from a neutron strikes to a transistor alter the memory state or the logic state of o... [more] |
CPSY2009-8 DC2009-8 pp.43-48 |