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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| HWS, VLD | 2023-03-02 11:50 |
Okinawa | (Primary: On-site, Secondary: Online) |
Automatic Synthesis of Decoupled Data Orchestration in High-Level Synthesis Masayuki Usui, Shinya Takamaeda (UTokyo)  VLD2022-90 HWS2022-61 |
We automatically decouple data orchestration mechanisms in explicit data orchestration to facilitate accelerator design.... [more] | VLD2022-90 HWS2022-61 pp.103-108 |
| SP, IPSJ-SLP, EA, SIP [detail] | 2023-03-01 11:20 |
Okinawa | (Primary: On-site, Secondary: Online) |
An Investigation of Text-to-Speech Synthesis Using Voice Conversion and x-vector Embedding Sympathizing Emotion of Input Audio for Spoken Dialogue Systems Shunichi Kohara, Masanobu Abe, Sunao Hara (Okayama Univ.) EA2022-109 SIP2022-153 SP2022-73 |
In this paper, we propose a Text-to-Speech synthesis method to synthesize the same emotional expression as the input spe... [more] | EA2022-109 SIP2022-153 SP2022-73 pp.203-208 |
| IPSJ-SLDM, RECONF, VLD [detail] | 2023-01-23 10:30 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University (Primary: On-site, Secondary: Online) |
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79 |
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] | VLD2022-56 RECONF2022-79 pp.1-6 |
| IE, ITS, ITE-AIT, ITE-ME, ITE-MMS [detail] | 2022-02-22 14:25 |
Online | Online | Development of a Real Camera System with High-Level Synthesis Hardware of Median-Based Dynamic Background Subtraction Kohei Shinyamada, Akira Yamawaki (Kyutech) ITS2021-61 IE2021-70 |
In this study, we developed a median-based dynamic background subtraction image processing system equipped with a real c... [more] | ITS2021-61 IE2021-70 pp.214-218 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:20 |
Online | Online | Full Hardware Implementation of RTOS-Based Systems Using General-Purpose High-Level Synthesizer Takuya Ando, Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2021-51 CPSY2021-20 RECONF2021-59 |
This article proposes a method for implementing a whole RTOS-based system as hardware using general-purpose high-level s... [more] | VLD2021-51 CPSY2021-20 RECONF2021-59 pp.13-18 |
| RECONF, VLD, CPSY, IPSJ-ARC, IPSJ-SLDM [detail] | 2022-01-24 10:45 |
Online | Online | Design of Inter-Task Communication Modules for Full Hardware Implementation of RTOS-Based Systems Yukino Shinohara, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2021-52 CPSY2021-21 RECONF2021-60 |
This paper presents hardware implementation of inter-task communication functions of RTOS, in the scheme where all the t... [more] | VLD2021-52 CPSY2021-21 RECONF2021-60 pp.19-24 |
| ICTSSL, IEE-SMF, IN | 2021-10-22 11:15 |
Online | Online | [Memorial Lecture]
Design and Development of ICT for Social Expectation Discovery Research Munenari Inoguchi (Univ. of Toyama) ICTSSL2021-27 |
In 2020, the Science and Technology Basic Law was amended, and the promotion of research in the humanities and social sc... [more] | ICTSSL2021-27 pp.54-59 |
| HWS, VLD [detail] | 2021-03-03 14:55 |
Online | Online | Aggregating Service Functions in Full Hardware Implementation of RTOS-Based Systems Iori Muguruma, Nagisa Ishiura, Takuya Ando (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) VLD2020-75 HWS2020-50 |
This article presents a revised architecture for full-hardware implementation of RTOS-based systems. In the previous m... [more] |
VLD2020-75 HWS2020-50 pp.38-43 |
| SP, EA, SIP | 2020-03-03 09:00 |
Okinawa | Okinawa Industry Support Center (Cancelled but technical report was issued) |
A Study for HMM-based embedded speech synthesis using a large-scale speech corpus Nobuyuki Nishizawa, Tomohiro Obara, Hiromi Ishizaki (KDDI Research, Inc.) EA2019-141 SIP2019-143 SP2019-90 |
This study shows that our speech synthesis system based on HMM speech synthesis for embedded devices can perform real-ti... [more] | EA2019-141 SIP2019-143 SP2019-90 pp.231-236 |
| RCC | 2020-01-27 14:45 |
Osaka | Neural ordinary differential equations-based static output feedback stabilization Koki Kobayashi (NAIST), Masaki Ogura (Osaka Univ), Masako Kishida (NII), Wadayama Tadashi (NITech), Kenji Sugimoto (NAIST) RCC2019-73 |
The static output-feedback stabilization problem is one of the basic controller synthesis problem in the systems and con... [more] | RCC2019-73 pp.19-22 |
|
| IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] | 2020-01-23 11:50 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Binary Synthesis from RISC-V Executables Shoki Hamana, Nagisa Ishiura (Kwansei Gakuin Univ.) VLD2019-71 CPSY2019-69 RECONF2019-61 |
This article presents a method of synthesizing hardware from RISC-V binary codes. RISC-V is an open source instruction s... [more] | VLD2019-71 CPSY2019-69 RECONF2019-61 pp.111-115 |
| ISEC, SITE, ICSS, EMM, HWS, BioX, IPSJ-CSEC, IPSJ-SPT [detail] | 2019-07-24 13:45 |
Kochi | Kochi University of Technology | Design Space Search Applying Bayesian Optimization to High-level Design Flow Ryohei Nakayama (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo) ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 |
Now that circuit scale is increasing, high-level synthesis technology that designs circuits using high-level programming... [more] | ISEC2019-57 SITE2019-51 BioX2019-49 HWS2019-52 ICSS2019-55 EMM2019-60 pp.369-374 |
| NC, IBISML, IPSJ-MPS, IPSJ-BIO [detail] | 2019-06-17 13:25 |
Okinawa | Okinawa Institute of Science and Technology | Analysis of periodic orbits in digital maps by a self-organizaition synthesis method Yuya Sawano, Toshimichi Saito (HU) NC2019-2 |
Self-organizing learning of digital map is considered in this paper. The digital map is a simple digital dynamical sys... [more] |
NC2019-2 pp.3-7 |
| HWS, VLD | 2019-03-01 10:00 |
Okinawa | Okinawa Ken Seinen Kaikan | Synthesis of Full Hardware Implementation of RTOS-Based Systems Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM) VLD2018-122 HWS2018-85 |
This paper presents a method of automatically synthesizing a hardware design from a set of source codes for a real-time... [more] |
VLD2018-122 HWS2018-85 pp.175-180 |
| RECONF | 2018-05-24 15:20 |
Tokyo | GATE CITY OHSAKI | A design of autoscale mechanism using high level synthesis tool for autonomous distributed system Daichi Teruya, Hironori Nakajo (TUAT) RECONF2018-9 |
Since cloud computing has become widespread for various purposes, it is drawing attention to use FPGAs. When utilizing ... [more] |
RECONF2018-9 pp.45-50 |
| SIP, EA, SP, MI (Joint) [detail] |
2018-03-20 16:45 |
Okinawa | Geometry calibration method based on point-cloud registration for a portable X-ray system Takuya Kato, Takashi Ohnishi, Masashi Sekine, Hideaki Haneishi (Chiba Univ.) MI2017-106 |
Tomosynthesis is a medical image modality that can acquire tomographic images at low doses compared to X-ray CT. In this... [more] | MI2017-106 pp.145-148 |
|
| MSS, NLP (Joint) |
2018-03-13 16:10 |
Osaka | Synchronous/Asynchronous Decentralized Event-Triggered Control for Cyber-Physical Systems Kyohei Nakajima, Koichi Kobayashi, Yuh Yamashita (Hokkaido Univ.) MSS2017-87 |
In control of cyber-physical systems, it is important to achieve both a low communication load and a high control perfor... [more] | MSS2017-87 pp.53-56 |
|
| VLD, HWS (Joint) |
2018-02-28 13:55 |
Okinawa | Okinawa Seinen Kaikan | Congestion Aware High Level Synthesis Design Flow with Source Compiler Masato Tatsuoka, Mineo Kaneko (JAIST) VLD2017-96 |
When we use a high level synthesis (HLS) tool, the optimization of input code is necessary for obtaining an optimized ... [more] | VLD2017-96 pp.43-48 |
| IPSJ-ARC, VLD, CPSY, RECONF, IPSJ-SLDM [detail] | 2018-01-18 17:00 |
Kanagawa | Raiosha, Hiyoshi Campus, Keio University | Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) VLD2017-75 CPSY2017-119 RECONF2017-63 |
This paper presents a distributed memory architecture for dedicated hardware automatically synthesized from Erlang prog... [more] |
VLD2017-75 CPSY2017-119 RECONF2017-63 pp.77-82 |
| SP, SIP, EA | 2017-03-02 09:00 |
Okinawa | Okinawa Industry Support Center | [Poster Presentation]
Individuality-Preserving HMM Sound Synthesis System for Articulation Disorders Reina Ueda (Kobe Univ.), Tetsuya Takiguchi (Kobe Univ./JST PRESTO), Yasuo Ariki (Kobe Univ.) EA2016-136 SIP2016-191 SP2016-131 |
This paper presents a speech synthesis method for a person with an articulation disorder resulting from the athetoid typ... [more] | EA2016-136 SIP2016-191 SP2016-131 pp.301-306 |
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