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All Technical Committee Conferences (Searched in: All Years)
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Search Results: Conference Papers |
Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
SDM |
2019-11-08 13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Three-dimensional accurate TCAD simulation of trench-gate Si-IGBTs Masahiro Watanabe, Naoyuki Shigyo, Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima (Tokyo Tech.), Katsumi Satoh (Mitsubishi Electric Corp.), Tomoko Matsudai (Toshiba Electronic Devices & Storage Corp.), Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi (The University of Tokyo), Iriya Muneta, Hitoshi Wakabayashi (Tokyo Tech.), Akira Nakajima (AIST), Shin-ichi Nishizawa (Kyushu University, Kasuga), Kazuo Tsutsui (Tokyo Tech.), Toshiro Hiramoto (The University of Tokyo), Hiromichi Ohashi, Hiroshi Iwai (Tokyo Tech.) SDM2019-77 |
In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obta... [more] |
SDM2019-77 pp.45-48 |
SDM |
2019-01-29 09:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
[Invited Talk]
Multidomain Dynamics of Ferroelectric Polarization in Negative Capacitance State and its Impacts on Performances of Field-Effect Transistors Hiroyuki Ota, Tsutomu Ikegami, Koichi Fukuda, Junichi HattoriI, Hidehiro Asai, Kazuhiko Endo, Shinji Migita (AIST), Akira Toriumi (The Univ. of Tokyo) SDM2018-81 |
In this paper, we clarified the multidomain dynamics of ferroelectric polarization in the Negative Capacitance Field-Eff... [more] |
SDM2018-81 pp.1-4 |
VLD, HWS (Joint) |
2018-02-28 17:20 |
Okinawa |
Okinawa Seinen Kaikan |
Evaluation of a Radiation-Hardened Method and Soft Error Resilience on Stacked Transistors in 28/65 nm FDSOI Processes Haruki Maruoka, Kodai Yamada, Mitsunori Ebara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2017-103 |
The continuous downscaling of transistors has resulted in an increase of reliability issues for semiconductor chips. In ... [more] |
VLD2017-103 pp.85-90 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:15 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-49 DC2016-43 |
According to the Moore's law, LSIs are miniaturized and the
reliability of LSIs is degraded. To improve the tolerance ... [more] |
VLD2016-49 DC2016-43 pp.31-36 |
VLD, DC, CPSY, RECONF, CPM, ICD, IE (Joint) [detail] |
2016-11-28 14:40 |
Osaka |
Ritsumeikan University, Osaka Ibaraki Campus |
Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT) VLD2016-50 DC2016-44 |
The impact of soft errors has been serious with process scaling of integrated circuits. Simulation methods for soft erro... [more] |
VLD2016-50 DC2016-44 pp.37-41 |
SDM, VLD |
2007-10-30 15:25 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Analysis of strain-dependent hole transport characteristics in bulk Ge-pMOSFETs Hiroshi Takeda (NEC), Takeo Ikezawa, Michihito Kawada (NIS), Masami Hane (NEC) VLD2007-58 SDM2007-202 |
Self-consistent full-band Monte Carlo (with multi-subbands) device simulations were performed to clarify the mechanism o... [more] |
VLD2007-58 SDM2007-202 pp.37-41 |
SDM, VLD |
2006-09-26 13:00 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations Takahisa Kanemura, Takashi Izumida, Nobutoshi Aoki, Masaki Kondo, Sanae Ito, Toshiyuki Enda, Kimitoshi Okano, Hirohisa Kawasaki, Atsushi Yagishita, Akio Kaneko, Satoshi Inaba, Mitsutoshi Nakamura, Kazunari Ishimaru, Kyoichi Suguro, Kazuhiro Eguchi (Toshiba Corp.) |
We discussed the optimization of structure of bulk-FinFETs and ion implantations by using 3-D process and device simulat... [more] |
VLD2006-43 SDM2006-164 pp.25-29 |
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