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All Technical Committee Conferences (Searched in: All Years)
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2022-03-10 10:50 |
Online | Online | A Test Generatoin Method to Improve Diagonostic Resolution Based on Fault Sensitization Coverage Yuya Chida, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.)  CPSY2021-57 DC2021-91 |
As one of test generation methods to achieve high defect coverage, n-detection test generation methods have been propose... [more] | CPSY2021-57 DC2021-91 pp.73-78 |
| HWS, VLD [detail] | 2020-03-06 14:30 |
Okinawa | Okinawa Ken Seinen Kaikan (Cancelled but technical report was issued) |
A Test Generation Method for Resistive Open Faults Using Partial MAX-SAT solver Hiroshi Yamazaki, Yuta Ishiyama, Tatsuma Matsuta, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) VLD2019-131 HWS2019-104 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | VLD2019-131 HWS2019-104 pp.215-220 |
| VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC (Joint) [detail] |
2019-11-14 16:35 |
Ehime | Ehime Prefecture Gender Equality Center | Test Generation for Hardware Trojan Detection Using the Delay Difference of a Pair of Independent Paths Suguru Rikino, Yushiro Hiramoto, Satoshi Ohtake (Oita Univ.) VLD2019-46 DC2019-70 |
Hardware Trojan detection is important to ensure security of LSIs. If a hardware Trojan is inserted in a signal line o... [more] |
VLD2019-46 DC2019-70 pp.151-155 |
| CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] | 2019-03-18 09:00 |
Kagoshima | Nishinoomote City Hall (Tanega-shima) | A Test Generation Method for Resistive Open Faults Using MAX-SAT Problem Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.), Masayuki Arai (Nihon Univ.), Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) CPSY2018-117 DC2018-99 |
In VLSI testing, stuck-at fault model and transition fault model have been widely used. However, with advance of semicon... [more] | CPSY2018-117 DC2018-99 pp.315-320 |
| DC | 2019-02-27 09:50 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | A Low Capture Power Oriented X-Identification Method Mimicking Fault Propagation Paths of Capture Safe Test Vectors Kenichiro Misawa, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyouto Sangyo Univ) DC2018-73 |
Low power oriented don't care (X) identification and X filling methods have been proposed to reduce the numbers of captu... [more] | DC2018-73 pp.13-18 |
| DC | 2011-02-14 11:00 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | An Analysis of Critical Paths for Field Testing with Process Variation Consideration Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) DC2010-61 |
Recently, it has the problem that good VLSIs in production testing become defective VLSIs in the fields because small de... [more] | DC2010-61 pp.13-19 |
| ICD, CPM | 2005-01-28 16:45 |
Tokyo | Kikai-Shinko-Kaikan Bldg. | Development of Multiple Fault Diagnosis Based on Path-Tracing for Logic LSIs Yukihisa Funatsu, Hiroshi Sumitomo, Kazuki Shigeta, Toshio Ishiyama (NECEL) |
For recent highly integrated and shrunk LSIs, CAD-based fault diagnosis technology which supports physical failure analy... [more] | CPM2004-174 ICD2004-219 pp.71-76 |
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