Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
ISEC |
2021-05-19 15:00 |
Online |
Online |
[Invited Talk]
Efficiency and Accuracy Improvements of Secure Floating-Point Addition over Secret Sharing (from IWSEC 2020) Kota Sasaki (The Univ. of Tokyo), Koji Nuida (Kyushu Univ.) ISEC2021-8 |
In secure multiparty computation (MPC), floating-point numbers should be handled in many potential applications, but the... [more] |
ISEC2021-8 p.33 |
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] |
2015-03-07 13:25 |
Kagoshima |
|
Design and Evaluation of a Floating-point Multiplier with Online Error Detection by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) CPSY2014-181 DC2014-107 |
A floating-point multiplier with reduced precision error detection is proposed.
It uses a truncated multiplier for chec... [more] |
CPSY2014-181 DC2014-107 pp.125-130 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita |
B-ConPlaza |
An extended precision floating-point adder with 104-bit significand using two double precision floating-point adders Hiroyuki Yataka, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-75 |
In recent years, high speed and high precision computing is increasingly needed.
Hardware support for IEEE754 compliant... [more] |
CPSY2014-75 pp.19-23 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita |
B-ConPlaza |
A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.) CPSY2014-76 |
Complex operations are used in scientific computing and signal processing.
Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
DC |
2014-06-20 15:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Floating-point Multiplier with Reduced Precision Error Checking by Partial Duplication Nobutaka Kito (Chukyo Univ.), Kazushi Akimoto, Naofumi Takagi (Kyoto Univ.) DC2014-15 |
We propose a floating-point multiplier with reduced precision error checking.
The multiplier uses a truncated multiplie... [more] |
DC2014-15 pp.33-38 |
ITS, IE, ITE-AIT, ITE-HI, ITE-ME [detail] |
2014-02-17 10:20 |
Hokkaido |
Hokkaido Univ. |
Relaxation of Restriction on HDR Image Formats for A Fixed-Point Tone Mapping Operation Atsushi Tashiro (Tokyo Metropolitan Univ), Tatsuya Murofushi, Toshiyuki Dobashi (Tokyo Metropolitan Univ.), Masahiro Iwahashi (Nagaoka Univ. of Tech.), Hitoshi Kiya (Tokyo Metropolitan Univ.) ITS2013-34 IE2013-99 |
This paper proposes an integer tone mapping operation (TMO) with fixed-point arithmetic
for high dynamic range (HDR) im... [more] |
ITS2013-34 IE2013-99 pp.25-30 |
SIP, CAS, MSS, VLD |
2013-07-11 11:00 |
Kumamoto |
Kumamoto Univ. |
A Fixed-Point Tone Mapping Operation for HDR Images Expressd in Floating-Point Data Toshiyuki Dobashi, Tatsuya Murofushi (Tokyo Metropolitan Univ.), Masahiro Iwahashi (Nagaoka Univ. of Tech.), Hitoshi Kiya (Tokyo Metropolitan Univ.) CAS2013-7 VLD2013-17 SIP2013-37 MSS2013-7 |
This paper proposes a tone mapping operation (TMO) with fixed-point arithmetic for high dynamic range (HDR) images expre... [more] |
CAS2013-7 VLD2013-17 SIP2013-37 MSS2013-7 pp.37-41 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] |
2013-03-14 15:30 |
Nagasaki |
|
Evaluation Environment for Configuration of Floating-Point Unit Arrays Yuya Itoh, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) CPSY2012-94 DC2012-100 |
A floating-point unit array that is constructed by connecting floating-point units, is expected to be an excellent archi... [more] |
CPSY2012-94 DC2012-100 pp.253-258 |
ITS, IE, ITE-AIT, ITE-HI, ITE-ME [detail] |
2013-02-18 13:40 |
Hokkaido |
Hokkaido Univ. |
AN INTEGER OPERATION OF GLOBAL TONE MAPPING FOR HDR IMAGES Tatsuya Murofushi (Tokyo Metropolitan Univ.), Masahiro Iwahashi (Nagaoka Univ. of Tech.), Hitoshi Kiya (Tokyo Metropolitan Univ.) ITS2012-38 IE2012-118 |
This paper proposes a new tone mapping operation which is implemented in integer input and integer output.
A tone mappi... [more] |
ITS2012-38 IE2012-118 pp.221-226 |
SCE |
2012-07-19 11:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design of a 2bit Bit-Slice Half-Precision Floating-Point Multiplier Using SFQ Circuits Yohei Naruse (Kyoto Univ.), Nobutaka Kito (Chukyo Univ.), Naofumi Takagi (Kyoto Univ.) SCE2012-12 |
Single flux quantum (SFQ) circuits are expected as next-generation circuits.
Arithmetic circuits using SFQ circuits ha... [more] |
SCE2012-12 pp.19-23 |
RECONF |
2012-05-29 13:10 |
Okinawa |
Tiruru (Naha Okinawa, Japan) |
Implementation and Evaluation of FPGA-based Data Compression Hardware of Floating-Point Data-Stream Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.) RECONF2012-7 |
This paper presents FPGA-based implementation and performance analysis of the hardware for lossless compression of a flo... [more] |
RECONF2012-7 pp.37-42 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-29 09:25 |
Miyazaki |
NewWelCity Miyazaki |
Evaluation of Out-Of-Order System for FaSTAR Implemented on FPGAs Takayuki Akamine, Kenta Inakagata (Keio Univ.), Yasunori Osana (Ryukyu Univ.), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.) RECONF2011-45 |
Computational Fluid Dynamics is an important tool to design aircraft components. FaSTAR is one of the most recent CFD pr... [more] |
RECONF2011-45 pp.25-30 |
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2011-11-30 09:00 |
Miyazaki |
NewWelCity Miyazaki |
A Circuit Partitioning Strategy for 3-D Integrated Floating-point Multipliers Kazushige Kawai, Jubee Tada (Yamagata Univ.), Ryusuke Egawa, Hiroaki Kobayashi (Tohoku Univ.), Gensuke Goto (Yamagata Univ.) CPM2011-162 ICD2011-94 |
Three-dimensional (3-D) integration technologies are attractive for enhancing the speed of the arithmetic circuits. To i... [more] |
CPM2011-162 ICD2011-94 pp.67-72 |
RECONF |
2010-09-16 15:00 |
Shizuoka |
Shizuoka University (Faculty of Eng., Hall 2) |
Hardware Lossless-Compressors of Floating-Point Data Streams to Enhance Memory Bandwidth Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.) RECONF2010-24 |
This paper presents an FPGA-based lossless compressor that directly compresses floating-point data streams to enhance th... [more] |
RECONF2010-24 pp.37-42 |
SCE |
2010-07-22 14:05 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm2 Nb Advanced Process Yasuhiro Shimamura, Toshiki Kainuma, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) SCE2010-22 |
We have been developing a large-scale reconfigurable data-path (LSRDP) using single-flux-quantum (SFQ) circuit to realiz... [more] |
SCE2010-22 pp.47-52 |
SCE |
2009-10-20 13:50 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design of SFQ Floating-Point Units Using Nb Advanced Process Toshiki Kainuma, Yasuhiro Shimamura, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama Nat. Univ.), Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) SCE2009-19 |
We are developing a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SFQ) circuits, which ... [more] |
SCE2009-19 pp.13-18 |
SCE |
2008-01-25 15:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Design and implementation of the SFQ half-precision floating point adder Heejoung Park, Yuki Yamanashi, Kazuhiro Taketomi, Nobuyuki Yoshikawa (Yokohama National Univ.), Masamitsu Tanaka, Koji Obata, Yuki Itou, Akira Fujimaki, Naofumi Takagi, Kazuyoshi Takagi (Nagoya Univ.) |
A new project was started to develop a large-scale reconfigurable data-path (LSRDP) based on the single-flux-quantum (SF... [more] |
SCE2007-31 pp.35-40 |
NLP |
2007-03-06 10:15 |
Miyagi |
|
Resistive ladder D/A converters for floating-point representation Hiroyuki Tomura, Toshimichi Saito (Hosei Univ.) |
This paper presents a circuit model of a floating-point resistive ladder D/A converter.
In the circuit, the mantissa i... [more] |
NLP2006-157 pp.17-20 |
RECONF |
2005-05-13 11:30 |
Kyoto |
Kyoto University |
Developing a parallel reconfigurable system for physics computations Tsuyoshi Hamada, Naohito Nakasato (RIKEN) |
We have developped PROGRAPE-3P1, a reconfigurable system for particle based simulations. The peak spead of PROGRAPE-3P1 ... [more] |
RECONF2005-20 pp.31-36 |