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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 354  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
NS 2023-10-04
Hokkaido Hokkaidou University + Online
(Primary: On-site, Secondary: Online)
Study of high availability VPN gateway with hardware accelerator
Kotomi Takahashi, Katsuma Miyamoto, Hiroki kano, Shinya Kawano, Yasuyuki matsuoka (NTT) NS2023-75
(To be available after the conference date) [more] NS2023-75
RECONF 2023-09-14
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Building Simulation Environment for Reconfigurable Virtual Accelerator (ReVA)
Shunya Kawai, Kazuki Yaguchi, Eriko Maeda (TUAT), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) RECONF2023-21
In this paper,we propose a simulation environment using Post-Implementation Simulation of Vivado to confirm functions of... [more] RECONF2023-21
RECONF 2023-09-14
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator using High-Speed Data Transfer with the Vector Register Sharing Mechanism
Go Akamatsu, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi Miyoshi (Wasalabo), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-24
Vector processors can load lots of data and perform operations in parallel.
The Vector Register Sharing Mechanism, prop... [more]
RECONF 2023-09-15
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Implementation and Evaluation of a Hardware Accelerator via Vector Register Sharing Mechanism for Massive Data Transfer
Michiya Kato, Tomoaki Tanaka (TUAT), Kiyofumi Tanaka (JAIST), Yasunori Osana (Kumamoto Univ.), Takefumi MIyoshi (Wasarabo LLC), Jubee Tada (Yamagata Univ.), Hironori Nakajo (TUAT) RECONF2023-29
Vector Register Sharing Mechanism is a method of data transfer by connecting some of the vector registers in the vector ... [more] RECONF2023-29
RECONF 2023-09-15
Tokyo Tokyo University of Agriculture and Technology Koganei campus
(Primary: On-site, Secondary: Online)
Abstraction of Processor-FPGA Communication in Reconfigurable Virtual Accelerator (ReVA)
Eriko Maeda, Kazuki Yaguchi, Shunya Kawai, Daichi Teruya (TUAT), Yasunori Osana (Kumamoto Univ.), Takehumi Miyoshi (Wasalabo), Hironori Nakajo (TUAT) RECONF2023-30
In recent years, hardware acceleration for HPC and AI has become a challenge due to the lack of resources and the comple... [more] RECONF2023-30
RECONF 2023-08-04
Hokkaido Hakodate Arena
(Primary: On-site, Secondary: Online)
An Elastic FPGA-based Accelerator for Bayesian Network Structure Learning
Ryota Miyagi (The Univ. of Tokyo), Ryota Yasudo (Kyoto Univ.), Kentaro Sano (RIKEN), Hideki Takase (The Univ. of Tokyo) RECONF2023-15
A Bayesian network is a powerful model for representing knowledge involving uncertainty within discrete random variables... [more] RECONF2023-15
EMM, BioX, ISEC, SITE, ICSS, HWS, IPSJ-CSEC, IPSJ-SPT [detail] 2023-07-24
Hokkaido Hokkaido Jichiro Kaikan Non-profiled Side-channel Attacks by using Clustering Scores in Deep Learning model (1) -- Attacks by using Auto Encoder against hardware-implemented AES --
Mizuki Nagahisa, Fukuda Yuta, Yoshida Kota, Fujino Takeshi (Ristumei Univ) ISEC2023-14 SITE2023-8 BioX2023-17 HWS2023-14 ICSS2023-11 EMM2023-14
In 2019, Differential Deep Learning Analysis (DDLA) was proposed as a deep-learning based side-channel attack in non-pro... [more] ISEC2023-14 SITE2023-8 BioX2023-17 HWS2023-14 ICSS2023-11 EMM2023-14
MSS, CAS, SIP, VLD 2023-07-06
(Primary: On-site, Secondary: Online)
Performance Improvement by Memory access and Process-level Pipelining for High-level Synthesized Sprite Drawing Hardware
Yuka Otani, Akira Yamawaki (Kyutech) CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
A mobile terminal with hardware reconfigurability can achieve higher performance and lower power consumption by performi... [more] CAS2023-3 VLD2023-3 SIP2023-19 MSS2023-3
HWS 2023-04-14
(Primary: On-site, Secondary: Online)
Exploration of hardware Trojan detection through power supply current simulation
Takafumi Oki, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) HWS2023-1
The recent development of information and communication technology has increased the demand for integrated circuit (IC) ... [more] HWS2023-1
HWS 2023-04-15
(Primary: On-site, Secondary: Online)
An AES Cryptographic Processor with Partial Re-Keying Scheme Utilizing Physical Attack Sensor
Ryuki Ikemoto, Soichiro Fujii (Osaka Univ.), Yuki Yamashita, Makoto Nagata (Kobe Univ.), Jun Shiomi, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ.) HWS2023-9
We propose a partial secret key update method for AES cryptography using sensors that can detect physical attacks on cry... [more] HWS2023-9
CCS 2023-03-26
Hokkaido RUSUTSU RESORT Hardware Implementation of Predictive Coding Networks based on the Free Energy Principle
Naruki Hagiwara, Takafumi Kunimi, Kota Ando (Hokkaido Univ.), Megumi Akai (Hokkaido Univ./Osaka Univ.), Tetsuya Asai (Hokkaido Univ.) CCS2022-69
Agents form generative models in the brain through perception and actions for adapting to the external environment. In t... [more] CCS2022-69
NLP, MSS 2023-03-17
(Primary: On-site, Secondary: Online)
Chaotic Response of Hardware Small World Neural Network with STDP
Takuto Yamaguchi, Katsutoshi Saeki, Yoshiki Sasaki (Nihon Univ.) MSS2022-106 NLP2022-151
The role of chaotic activity in the brain function is still unclarified. However, it is possible to estimate the role by... [more] MSS2022-106 NLP2022-151
HWS, VLD 2023-03-01
(Primary: On-site, Secondary: Online)
Programmable Binary Hyperdimensional Computing Accelerator for Low Power Devices
Yuya Isaka (NAIST), Nau Sakaguchi (SJSU), Michiko Inoue (NAIST), Michihiro Shintani (KIT) VLD2022-76 HWS2022-47
Hyperdimensional computing (HDC) can perform various cognitive tasks efficiently by mapping data to hyperdimensional vec... [more] VLD2022-76 HWS2022-47
HWS, VLD 2023-03-02
(Primary: On-site, Secondary: Online)
Secure Cache System against On-Chip Threats
Keisuke Kamahori, Shinya Takamaeda (UTokyo) VLD2022-95 HWS2022-66
In this paper, we propose a new threat model for secure processor design that considers on-chip threats.
Also, we desi... [more]
VLD2022-95 HWS2022-66
HWS, VLD 2023-03-02
(Primary: On-site, Secondary: Online)
Hiding Memory Structure for IP Protection
Sun Tanaka, Shinya Takamaeda (UTokyo) VLD2022-96 HWS2022-67
This paper proposes a concept and a method of hiding memory structure for IP protection. [more] VLD2022-96 HWS2022-67
HWS, VLD 2023-03-04
(Primary: On-site, Secondary: Online)
Threat of EM Information Leakage from Speakerphones Due to IEMI and Suppression Indexes for EMC Countermeasures
Seiya Takano, Yuichi Hayashi (NAIST) VLD2022-120 HWS2022-91
Threats of causing forced electromagnetic information leakage by irradiating devices with electromagnetic waves have bee... [more] VLD2022-120 HWS2022-91
HWS, VLD 2023-03-04
(Primary: On-site, Secondary: Online)
Masaru Mashiba, Kazuki Monta (Kobe Univ.), Takaaki Okidono (SCU), Takuzi Miki, Nagata Makoto (Kobe Univ.) VLD2022-121 HWS2022-92
With the development of IoT, security is becoming increasingly important. Confidential information and other information... [more] VLD2022-121 HWS2022-92
SP, IPSJ-SLP, EA, SIP [detail] 2023-03-01
(Primary: On-site, Secondary: Online)
Low-bit Image Restoration with Loop-unrolled ISTA
Shu Abe, Soushi Takahashi, Shogo Muramatsu (Niigata Univ) EA2022-125 SIP2022-169 SP2022-89
This study proposes a low-bit image restoration method based on a loop-unrolled network of Iterative Shrinkage Threshold... [more] EA2022-125 SIP2022-169 SP2022-89
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Partitioning and Distributing Circuit Using HLS Split Compilation Tool for Reconfigurable Virtual Accelerator (ReVA)
Kazuki Yaguchi, Eriko Maeda, Daichi Teruya (TUAT), Yasunori Osana (Univ. of the Ryukyus), Takefumi Miyoshi (WasaLabo), Hironori Nakajo (TUAT) VLD2022-57 RECONF2022-80
Currently, hardware acceleration with FPGAs is often used for accelerating computational processes in fields such as art... [more] VLD2022-57 RECONF2022-80
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
[Invited Talk] Can we say "No FPGA, No Smart City"? -- Let's declare if we do a smart city, we need FPGAs. --
Hiroaki Nishi (Keio Univ.) VLD2022-60 RECONF2022-83
From the perspective of a chair of standardization of technologies related to Smart City information infrastructure, we ... [more] VLD2022-60 RECONF2022-83
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