Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
HWS, ICD, VLD |
2025-03-06 14:25 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
Implementation Method and Circuit Fabrication for Photonic Circuits of Symmetric Key Cryptography Junko Takahashi, Shota Kita, Akihiko Shinya (NTT), Kazumaro Aoki (Bunkyo Univ), Koji Chida (Gunma Univ), Fumitaka Hoshino (Univ. of Nagasaki) |
(To be available after the conference date) [more] |
|
ET |
2025-03-01 11:35 |
Nagano |
Shinshu University Faculty of Education (Nagano) |
Discussion of the Legal Texts Expression Using Logic Circuits for Error-Based Simulation in the Learning Support System for Japanese Patent Act Takako Akakura (TUS), Toru Kano (Ibaraki Univ.), Takahito Tomoto (CIT), Koichiro Kato (KIT) |
(To be available after the conference date) [more] |
|
SDM, ICD, ITE-IST [detail] |
2024-08-05 11:25 |
Hokkaido |
Hokkaido Univ. Multimedia Education Bldg. 3F (Hokkaido, Online) (Primary: On-site, Secondary: Online) |
Performance Enhancement and Design Optimization of Analog-to-Digital Converters Utilizing Dynamic Logics Yuhao Xu, Ritaro Takenaka, Shuowei Li, Haoming Zhang, Tetsuya Iizuka (UTokyo) SDM2024-29 ICD2024-19 |
This paper presents a study on performance optimization techniques for SAR ADC by addressing the bottlenecks in speed pe... [more] |
SDM2024-29 ICD2024-19 pp.15-20 |
NLP, MSS |
2024-03-14 16:05 |
Misc. |
Kikai-Shinko-Kaikan Bldg. (Misc.) |
Functional Electrical Stimulation Device Using Wireless Sequential Circuit Central Pattern Generator Model Rikuto Nozu, Hiroyuki Torikai (Hosei Univ) MSS2023-97 NLP2023-149 |
In this study, we design a functional electrical stimulator using a wireless sequential logic circuit central pattern ge... [more] |
MSS2023-97 NLP2023-149 p.123 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2023-11-15 14:40 |
Kumamoto |
Civic Auditorium Sears Home Yume Hall (Kumamoto, Online) (Primary: On-site, Secondary: Online) |
A 183.4 nJ/inference 152.8 µW Single-Chip Wired-Logic DNN Processor for Always-On 35 Voice Commands Recognition Application Rei Sumikawa, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (UTokyo) VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 |
A 183.4-nJ/inference single-chip wired-logic DNN processor that is capable of recognizing all 35 commands defined in the... [more] |
VLD2023-39 ICD2023-47 DC2023-46 RECONF2023-42 pp.54-59 |
SCE |
2023-08-08 11:25 |
Kanagawa |
Yokohama National Univ. (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Low-Cost Sorting Network Circuits Based on Temporal Logic Using Single Flux Quantum Circuits Zeyu Han, Zongyuan Li, Yamanashi Yuki, Yoshikawa Nobuyuki (YNU) SCE2023-5 |
Sorting is important in various applications such as image processing and switching systems. Hardware cost and power con... [more] |
SCE2023-5 pp.22-27 |
SCE |
2023-08-08 13:50 |
Kanagawa |
Yokohama National Univ. (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Design of an rf-SQUID with π-Josephson junction for inverter function of directly coupled quantum-flux-parametron logic Wataru Komiya, Naoki Takeuchi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.) SCE2023-8 |
Adiabatic quantum-flux-parametron (AQFP) logic relies on magnetic transformer for propagation and inversion, which prese... [more] |
SCE2023-8 pp.39-44 |
SCE |
2023-08-08 15:15 |
Kanagawa |
Yokohama National Univ. (Kanagawa, Online) (Primary: On-site, Secondary: Online) |
Design and Implementation of Neuron Circuit Using Adiabatic Quantum-Flux-Parametron Logic Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Naoki Takeuchi (AIST/Yokohama National Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.) SCE2023-11 |
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient,high performance in... [more] |
SCE2023-11 pp.53-57 |
CCS, NLP |
2023-06-08 15:35 |
Tokyo |
Tokyo City Univ. (Tokyo) |
A place and route method in AQFP circuits using multi-objective optimization Syota Kasai, Hidehiro Nakano (Tokyo City Univ.) NLP2023-18 CCS2023-6 |
In recent years, research has been conducted on AQFP circuits, which are superconducting logic circuits that consume les... [more] |
NLP2023-18 CCS2023-6 pp.21-24 |
HWS, VLD |
2023-03-02 13:50 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
[Memorial Lecture]
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology Chenlin Shi, Shinobu Miwa (UEC), Tongxin Yang, Ryota Shioya (UOT), Hayato Yamaki, Hiroki Honda (UEC) VLD2022-92 HWS2022-63 |
In this paper, we propose CNFET7, the first open-source cell library for7-nm carbon nanotube field-effect transistor (CN... [more] |
VLD2022-92 HWS2022-63 p.110 |
SCE |
2023-01-20 13:45 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo, Online) (Primary: On-site, Secondary: Online) |
Design and Implementation of Power Consumption Reduction Binary Neural Networks Using Adiabatic Quantum-Flux-Parametron Logic Tomoharu Yamauchi, Hao San (Tokyo City Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.), Olivia Chen (Tokyo City Univ.) SCE2022-14 |
Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient,high performance in... [more] |
SCE2022-14 pp.6-11 |
SCE |
2023-01-20 14:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. (Tokyo, Online) (Primary: On-site, Secondary: Online) |
Introduction of a fluctuation mechanism of the oscillation frequency of the oscillator-based random number generator using Josephson oscillation Takeshi Onomi (Fukuoka Inst. Tech.) SCE2022-15 |
An oscillator-based true random number generator using superconducting single flux quantum circuits and Josephson oscill... [more] |
SCE2022-15 pp.12-16 |
VLD, DC, RECONF, ICD, IPSJ-SLDM [detail] |
2022-11-30 10:45 |
Kumamoto |
(Kumamoto, Online) (Primary: On-site, Secondary: Online) |
Prototype and evaluation of 4-input variable logic circuit with FGC using neuron CMOS inverter Shoma Ito, Daishi Nishiguchi, Masaaki Fukuhara (Tokai Univ.) VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 |
Logic elements of FPGA generally use Look-Up Table (LUT) circuits, and the most common types of LUT are 4-input and 6-in... [more] |
VLD2022-45 ICD2022-62 DC2022-61 RECONF2022-68 pp.150-155 |
ET |
2022-09-17 14:55 |
Hiroshima |
Hiroshima University and Online (Hiroshima, Online) (Primary: On-site, Secondary: Online) |
Proposal of Generating Propositional Logic Formulas Methods for Learning Support Systems of Intellectual Property Law Akihisa Tomita, Toru Kano, Takako Akakura (TUS) ET2022-18 |
The development and spread of information technology, called the 4th Industrial Revolution, has increased the value of i... [more] |
ET2022-18 pp.48-51 |
NC, IBISML, IPSJ-BIO, IPSJ-MPS [detail] |
2022-06-29 14:20 |
Okinawa |
(Okinawa, Online) (Primary: On-site, Secondary: Online) |
LSI implementation of analog CMOS majority circuit for neural network applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2022-27 IBISML2022-27 |
Majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. It can be applied to b... [more] |
NC2022-27 IBISML2022-27 pp.189-192 |
NLP, MICT, MBE, NC (Joint) [detail] |
2022-01-23 10:15 |
Online |
Online (Online) |
Analog CMOS implementation of majority logic for neuromorphic circuit applications Satoshi Ono, Satoshi Moriya, Yuka Kanke, Hideaki Yamamoto (Tohoku Univ.), Yasushi Yuminaka (Gunma Univ.), Shigeo Sato (Tohoku Univ.) NC2021-41 |
A majority logic circuit is a circuit whose output is the majority value of multiple binary inputs. In addition to its c... [more] |
NC2021-41 pp.45-48 |
SDM, ICD, ITE-IST [detail] |
2021-08-18 15:35 |
Online |
Online (Online) |
Evaluation of Side-channel Leakage on High-speed Asynchronous Successive Approximation Register AD Converters Ryozo Takahashi, Kazuki Monta, Takuji Miki, Makoto Nagata (Kobe Univ.) SDM2021-43 ICD2021-14 |
This paper presents an evaluation of security level on high-speed asynchronous successive approximation register (SAR) a... [more] |
SDM2021-43 ICD2021-14 pp.68-71 |
SCE |
2021-08-06 14:35 |
Online |
Online (Online) |
Study on adiabatic quantum-flux-parametron datapaths with feedback loops adopting delay-line clocking Taiki Yamae (Yokohama Natl. Univ./JSPS Research Fellow), Naoki Takeuchi, Nobuyuki Yoshikawa (Yokohama Natl. Univ.) SCE2021-4 |
Adiabatic quantum-flux-parametron (AQFP) is a superconductor logic family which can operate with low switching energy. S... [more] |
SCE2021-4 pp.14-18 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2021-03-26 11:00 |
Online |
Online (Online) |
An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91 |
Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis... [more] |
CPSY2020-61 DC2020-91 pp.67-72 |
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] |
2021-03-26 12:00 |
Online |
Online (Online) |
A Logic Locking Method Based on Anti-SAT at Register Transfer Level Atsuya Tsujikawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) CPSY2020-64 DC2020-94 |
In recent years, increasing circuit density, it has become difficult for only one semiconductor design company to design... [more] |
CPSY2020-64 DC2020-94 pp.85-90 |