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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 42  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
VLD, DC, CPSY, RECONF, CPM, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2017-11-08
12:55
Kumamoto Kumamoto-Kenminkouryukan Parea CPSY2017-45 Generally, HDL simulation is used for development and verification of processor design.
However, the simulation speed i... [more]
CPSY2017-45
pp.53-58
CPSY, DC, IPSJ-ARC
(Joint) [detail]
2016-08-09
10:30
Nagano Kissei-Bunka-Hall (Matsumoto) High Performance of Cache by Dynamic Control to Area Division
Maika Tone, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo (Mie Univ.) CPSY2016-19
Today, multi-core processor is widely used to improve performance of a processor.
However, memory access frequency of m... [more]
CPSY2016-19
pp.119-124
ICD, IE, VLD, IPSJ-SLDM [detail] 2015-10-27
09:50
Miyagi   [Invited Talk] Developments of Advanced Driver Assistance System (ADAS) and Image Recognition SoC
Takashi Miyamori (Toshiba), Seiya Ide (DENSO) VLD2015-34 ICD2015-47 IE2015-69
Recent years, Advanced Driver Assistance Systems, ADAS, such as an autonomous emergency braking for vehicles and pedestr... [more] VLD2015-34 ICD2015-47 IE2015-69
p.43
RECONF, CPSY, VLD, IPSJ-SLDM [detail] 2015-01-30
17:30
Kanagawa Hiyoshi Campus, Keio University A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC) VLD2014-152 CPSY2014-161 RECONF2014-85
The inductive-coupling 3D chip stacking technique has several advantages over TSV-based 3D stacking. For example, its ma... [more] VLD2014-152 CPSY2014-161 RECONF2014-85
pp.245-250
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-16
09:50
Okinawa   Voltage control considering the chip temperature in the three-dimensional stacked multi-core processors
Yu Fujita, Yusuke Koizumi, Rie Uno, Hideharu Amano (Keio Univ.) CPSY2013-109 DC2013-96
Cube-1 is a prototype heterogeneous multiprocessor using inductive coupling wireless TCI (Through Chip Interface). Since... [more] CPSY2013-109 DC2013-96
pp.241-246
CPSY, IPSJ-EMB, IPSJ-SLDM, DC [detail] 2014-03-16
13:40
Okinawa   Evaluation of Performance Improvement Rate on Multi-core Tender
Takahiro Yamamoto, Toshihiro Yamauchi, Hideo Taniguchi (Okayama Univ.) CPSY2013-115 DC2013-102
Multi-core processors are widely used in modern embeded systems because higher and higher processing throughput is requi... [more] CPSY2013-115 DC2013-102
pp.277-282
RECONF 2013-09-19
13:50
Ishikawa Japan Advanced Institute of Science and Technology A Packet Classifier using Parallel EVMDD(k) Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.) RECONF2013-34
A decision diagram machine~(DDM) is a special-purpose processor that
uses special instructions to evaluate a decision... [more]
RECONF2013-34
pp.85-90
VLD 2013-03-05
14:55
Okinawa Okinawa Seinen Kaikan A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) VLD2012-150
Parallel routing methods using various parallel computing environments have been proposed in existing studies for reduci... [more] VLD2012-150
pp.83-88
IE, SIP, ICD, VLD, IPSJ-SLDM [detail] 2012-10-19
11:00
Iwate Hotel Ruiz [Invited Talk] Development of Heterogeneous Multi-Core SoC ViscontiTM2 for Image Recognition Applications
Takashi Miyamori, Yasuki Tanabe, Moriyasu Banno (Toshiba) VLD2012-50 SIP2012-72 ICD2012-67 IE2012-74
Use of image recognition technologies in various products is rapidly expanding. For automotive applications, pedestrian ... [more] VLD2012-50 SIP2012-72 ICD2012-67 IE2012-74
pp.55-58
RECONF 2012-05-29
17:35
Okinawa Tiruru (Naha Okinawa, Japan) Development of Application for Heterogeneous Multi-Core Processor
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano (Keio Univ.), Ryuichi Sakamoto, Mitaro Namiki (Tkyo Univ. of Agri. and Tech.) RECONF2012-16
This paper describes the application development on a heterogeneous multi-core processor that consists of a CPU and acce... [more] RECONF2012-16
pp.89-94
VLD 2012-03-06
11:00
Oita B-con Plaza LSI Implementation of Heterogeneous Multi-Chip Processor for energy-saving Embedded Systems : COOL Chip
Hiroyuki Uchida, Michiya Hagimoto, Tomoyuki Morimoto, Nobuyuki Hikichi, Yukoh Matsumoto (TOPS Systems), Fumito Imura, Naoya Watanabe, Katsuya Kikuchi, Motohiro Suzuki, Hiroshi Nakagawa, Masahiro Aoyagi (AIST) VLD2011-122
The authors have suggested the low-power embedded heterogeneous multi-chip processor system: COOL Chip. We designed two ... [more] VLD2011-122
pp.13-17
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-02
16:15
Miyagi   Design and implementation of I/O control mechanism for heterogeneous multi-core processors
Yuki Kawaguchi, Kazutoshi Suito, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) CPSY2011-85 DC2011-89
Heterogeneous multi-core architecture that consists of processors, memory modules, and I/O devices with various sizes, f... [more] CPSY2011-85 DC2011-89
pp.91-96
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-02
16:45
Miyagi   Multi Core Task Mapping Method by Weight Control for Dependencies between Descendent Tasks
Noriaki Suzuki, Takahiro Kumura, Yuichi Nakamura (NEC) CPSY2011-86 DC2011-90
In this paper, we propose a task mapping method for AMP multi-core processors. In this method, weights of the dependenci... [more] CPSY2011-86 DC2011-90
pp.97-102
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
13:00
Miyagi   Development of a FPGA based performance evaluation system for a Ultra-Android prototype
Kenji Toda, Osamu Morikawa (AIST), Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Yasumori Hibi, Yukoh Matsumoto (Tops Systems) CPSY2011-91 DC2011-95
A performance evaluation system for Ultra-Android platform ,which achieves high performance and less energy consuming an... [more] CPSY2011-91 DC2011-95
pp.193-198
ICD, IPSJ-ARC 2012-01-20
13:10
Tokyo   [Invited Talk] Overview of High Performance Digital Processor Technology
Hiroo Hayashi (Toshiba Corp.) ICD2011-141
Evolution of high-performance digital technology has been ongoing. The author surveys the technology trends of high-per... [more] ICD2011-141
pp.73-76
ICD, IE, SIP, IPSJ-SLDM [detail] 2011-10-25
12:50
Miyagi Ichinobo(Sendai) [Invited Talk] Heterogeneous Many-Core Application Processor Architecture for Ultra-High-Quality Image Reproduction
Yukoh Matsumoto (TOPS) SIP2011-72 ICD2011-75 IE2011-71
We have developed CG Application-Domain Specific Heterogeneous Multi-Core architecture and its software for a Desk-Top R... [more] SIP2011-72 ICD2011-75 IE2011-71
pp.67-71
CPSY 2011-10-21
11:00
Hyogo   Design of a Method for Coexistence of 32/64-bit Kernels
Daiki Nakahara, Yoshinari Nomura, Hideo Taniguchi (Okayama Univ.) CPSY2011-29
As wide spreading of 64-bit CPUs, Operating System (OS) is changing its architecture-base from 32-bit to 64-bit. Softwar... [more] CPSY2011-29
pp.25-30
NS 2011-04-22
11:15
Fukui Fukui University Automatic generation method of communication code
Akihiro Miura, Yutaka Kawaguchi, Masaru Nagashima (Mitsubishi Electric Corp.) NS2011-13
In the embedded system, the use of the multi-core processor increases from the demand of making to high performance and ... [more] NS2011-13
pp.73-76
DC, CPSY 2011-04-12
16:35
Tokyo   Highly Flexible Task Tracer IP for the Real-Time OS on FPGA/SoC Environments
Yuji Takeda, Mamoru Ohara, Tadashi Okabe, Ken Sato (Tokyo Metro. Indust. Tech. Res. Inst.) CPSY2011-7 DC2011-7
Recently, the use of RTOS is advanced in a multi-core processor on FPGA/SoC, and to watch the task transitions is import... [more] CPSY2011-7 DC2011-7
pp.35-40
ICD, IPSJ-ARC 2011-01-21
11:40
Kanagawa Keio University (Hiyoshi Campus) Acceleration of Block Matching by using Multiple Alignments on Heterogeneous Multi-Core Processor
Yoshitaka Hiramatsu (Hitachi), Hasitha Muthumala Waidyasooriya, Masanori Hariyama (Tohoku Univ.), Tohru Nojiri, Kunio Uchiyama (Hitachi)
The large data-transfer time among different cores and data-supply time to arithmetic unit is a big problem in heterogen... [more] ICD2010-136
pp.57-62
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