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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 8 of 8  /   
Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2024-02-28
13:40
Tokyo Kikai-Shinko-Kaikan Bldg. Test Point Selection Method for Multi-Cycle BIST Using Deep Reinforcement Learning
Kohei Shiotani, Tatsuya Nishikawa, Shaoqi Wei, Senling Wang, Hiroshi Kai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) DC2023-98
Multi-cycle BIST is a test method that performs multiple captures for each scan pattern, proving effective in reducing t... [more] DC2023-98
pp.23-28
CPSY, DC, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC [detail] 2021-03-26
11:00
Online Online An Estimation Method of a Defect Types for Suspected Fault Lines in Logical Faulty VLSI Using Neural Networks
Natsuki Ota, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.), Yukari Yamauchi, Masayuki Arai (Nihon Univ.) CPSY2020-61 DC2020-91
Since fault diagnosis methods for specified fault models might cause misprediction and non-prediction, a fault diagnosis... [more] CPSY2020-61 DC2020-91
pp.67-72
VLD, DC, CPSY, RECONF, ICD, IE, IPSJ-SLDM, IPSJ-EMB, IPSJ-ARC
(Joint) [detail]
2019-11-14
16:10
Ehime Ehime Prefecture Gender Equality Center Analysis of Fault Detection Degradation Issue in Multi-cycle Test Scheme using Probabilistic Evaluation Method
Norihiro Nakaoka, Tomoki Aono, Sohshi Kudoh, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) VLD2019-45 DC2019-69
In order to ensure the functional safety of advanced autonomous driving systems, a power-on self-test
(POST) is require... [more]
VLD2019-45 DC2019-69
pp.145-150
DC 2019-02-27
14:05
Tokyo Kikai-Shinko-Kaikan Bldg. FF Toggle Control Point Selection Methods for Fault Detection Enhancement under Multi-cycle Testing
Tomoki Aono, Hanan T.Al-Awadhi, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas) DC2018-79
Multi-cycle Test is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power... [more] DC2018-79
pp.49-54
DC 2015-02-13
16:00
Tokyo Kikai-Shinko-Kaikan Bldg An Evalution of a Fault Diagnosis Method for Single Logical Faults Using Multi Cycle Capture Test Sets
Hideyuki Takano, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Koji Yamazaki (Meiji Univ.) DC2014-86
Multi-cycle capture testing has been proposed to improve test quality of scan testing. However, fault diagnosis for mult... [more] DC2014-86
pp.49-54
DC 2014-06-20
14:30
Tokyo Kikai-Shinko-Kaikan Bldg. Capture Power Evaluation for A Low Power BIST Method Using A TEG Chip
Toshiya Nishida (Kyushu Inst. of Tech.), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.) DC2014-13
Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay ... [more] DC2014-13
pp.21-26
DC 2014-02-10
16:00
Tokyo Kikai-Shinko-Kaikan Bldg. A Low Power Consumption Oriented Test Generation Method for Transition Faults Using Multi Cycle Capture Test Generation
Hiroshi Yamazaki, Yuto Kawatsure, Jun Nishimaki, Atsushi Hirai, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Koji Yamazaki (Meiji Univ) DC2013-89
High power dissipation can occur when the response to a test pattern is captured by flip-flops in at-speed scan testing,... [more] DC2013-89
pp.61-66
DC 2010-02-15
10:00
Tokyo Kikai-Shinko-Kaikan Bldg. Study on a Test Generation Method for Transition Faults Using Multi Cycle Capture Test
Hiroshi Ogawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyusyu Univ.), Koji Yamazaki (Meiji Univ.) DC2009-67
Overtesting induces unnecessary yield loss. Untestable faults have no effect on normal functions of circuits. However, i... [more] DC2009-67
pp.13-18
 Results 1 - 8 of 8  /   
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