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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
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Committee Date Time Place Paper Title / Authors Abstract Paper #
DC 2020-02-26
14:35
Tokyo   Power Analysis for Logic Area of LSI Including Memory Area
Yuya Kodama, Kohei Miyase, Daiki Takafuji, Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2019-93
Power consumption during LSI testing is higher than functional mode. Excessive IR-drop causes excessive delay, resulting... [more] DC2019-93
pp.43-48
DC 2019-02-27
10:15
Tokyo Kikai-Shinko-Kaikan Bldg. Analysis of the hotspot distribution in the LSI
Yudai Kawano, Kohei Miyase (Kyutech), Shyue-Kung Lu (NTUST), Xiaoqing Wen, Seiji Kajihara (Kyutech) DC2018-74
Performance degrading caused by high IR-drop in normal functional mode of LSI can be solved by improving power supply ne... [more] DC2018-74
pp.19-24
DC 2018-02-20
11:00
Tokyo Kikai-Shinko-Kaikan Bldg. Locating Hot Spots with Justification Techniques in a Layout Design
Yudai Kawano, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen (Kyutech) DC2017-80
In general, power consumption during LSI testing is higher than functional operation. Excessive power consumption in at-... [more] DC2017-80
pp.19-24
DC 2012-12-14
16:00
Fukui Aossa (Fukui) A Test Generation Model for Over-testing Alleviation and Its Application to Testing Based on Fault Acceptability
Masaaki Sakurada, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (HCU) DC2012-77
Over-testing, which is to judge fault-free chips as faulty ones, is a cause of the decrease in the effective yield of ch... [more] DC2012-77
pp.21-26
VLD, ICD, DC, IPSJ-SLDM 2005-12-02
09:55
Fukuoka Kitakyushu International Conference Center A Broadside Test Generation Method for Transition Faults in Partial Scan Circuits
Tsuyoshi Iwagaki (JAIST), Satoshi Ohtake, Hideo Fujiwara (NAIST)
This paper presents a broadside test generation method for
transition faults in partial scan circuits. In order to gene... [more]
VLD2005-77 ICD2005-172 DC2005-54
pp.7-12
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