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 Conference Papers (Available on Advance Programs)  (Sort by: Date Descending)
 Results 1 - 20 of 39  /  [Next]  
Committee Date Time Place Paper Title / Authors Abstract Paper #
IPSJ-SLDM, RECONF, VLD [detail] 2023-01-23
10:30
Kanagawa Raiosha, Hiyoshi Campus, Keio University
(Primary: On-site, Secondary: Online)
Multi-FPGA design environment using Cyberworkbench, a high-level synthesis tool
Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) VLD2022-56 RECONF2022-79
Multi-FPGA systems, in which multiple FPGA boards are directly connected via high-speed serial links, are attracting att... [more] VLD2022-56 RECONF2022-79
pp.1-6
IPSJ-SLDM, RECONF, VLD, CPSY, IPSJ-ARC [detail] 2019-01-31
15:05
Kanagawa Raiosha, Hiyoshi Campus, Keio University VLD2018-90 CPSY2018-100 RECONF2018-64 (To be available after the conference date) [more] VLD2018-90 CPSY2018-100 RECONF2018-64
pp.113-118
RECONF 2017-09-25
13:55
Tokyo DWANGO Co., Ltd. A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme
Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT) RECONF2017-25
The authors consider applying FPGA Dynamic Partial Reconfiguration (DPR) technique to carrier network equipment built wi... [more] RECONF2017-25
pp.19-24
RECONF 2016-09-06
10:30
Toyama Univ. of Toyama Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board
Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science) RECONF2016-33
Parallel processing by PC cluster and hardware acceleration by FPGA are useful technologies in a field of high performan... [more] RECONF2016-33
pp.39-44
RECONF 2015-09-18
14:30
Ehime Ehime University ZYNQ CLUSTER FOR CFD PARAMETRIC SURVEY
Naru Sugimoto, Hideharu Amano (Keio Univ.) RECONF2015-39
FaSTAR (Fast Aerodynamics Routines) is a state of the art CFD (Computational Fluid Dynamics) software package to enable ... [more] RECONF2015-39
pp.39-44
RECONF 2013-09-19
14:50
Ishikawa Japan Advanced Institute of Science and Technology Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration
Tomoaki Ukezono, Koichi Araki (JAIST) RECONF2013-36
In general, memories which can be referenced by associative search will enlarge hardware size and extend delay for refer... [more] RECONF2013-36
pp.97-102
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
10:30
Fukuoka Centennial Hall Kyushu University School of Medicine A Hardware Algorithm Using Dynamically Partially Reconfigurable FPGAs for Solving the Maximum Clique Problem of Large Graphs
Chikako Miura, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi (Hiroshima City Univ.) RECONF2012-53
In this paper, we propose a hardware algorithm to solve the maximum clique problem of large graphs, and show its impleme... [more] RECONF2012-53
pp.33-38
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2012-11-28
14:30
Fukuoka Centennial Hall Kyushu University School of Medicine An observational study on fault-avoidance methods using dynamic partial reconfiguration
Hiroaki Konoura (Osaka Univ.), Takashi Imagawa (Kyoto Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Masanori Hashimoto, Takao Onoye (Osaka Univ.) RECONF2012-59
Fault-avoidance methods using dynamic partial reconfiguration on reconfigurable devices are proposed for avoiding the em... [more] RECONF2012-59
pp.71-76
RECONF 2012-09-18
16:30
Shiga Epock Ritsumei 21, Ritsumeikan Univ. Study of "fine-grain dynamic partial reconfiguration mechanism" on FPGA
Kunihiro Ueda, Naoki Kawamoto, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-34
Dynamic and partial reconfiguration (DRP) on SRAM-based FPGAs has received increasing attention, since Xilinx Inc. start... [more] RECONF2012-34
pp.61-66
RECONF 2012-09-19
09:00
Shiga Epock Ritsumei 21, Ritsumeikan Univ. Effects of Power Saving by Dynamic Partial Reconfiguration in Video Shape Detection Processing
Naoki Kawamoto, Kunihiro Ueda, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.) RECONF2012-36
Some of recent FPGAs have the functionality of dynamic partial reconfiguration. By using this functionality, it is expec... [more] RECONF2012-36
pp.73-78
RECONF 2012-09-19
15:05
Shiga Epock Ritsumei 21, Ritsumeikan Univ. Speedup of soft error tolerance evaluation with bootstrap method for FPGA systems
Kohei Takano, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-45
SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU). Although techniques for ... [more] RECONF2012-45
pp.125-130
DC, CPSY
(Joint)
2012-08-03
09:30
Tottori Torigin Bunka Kaikan A development scheduling simulater for reconfiguable system
Takashige Uda, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2012-19
Reconfigurable Computing Systems (RC Systems) are used to high-speed applications processing. We have investigating the ... [more] CPSY2012-19
pp.61-66
RECONF 2012-05-29
15:10
Okinawa Tiruru (Naha Okinawa, Japan) Hard error avoidance for TMR module using dynamic relocation in an FPGA
Hiroki Tanaka, Yoshihiro Ichinomiya, Sadaki Usagawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2012-11
FPGA can recover from hard-error by reconfiguring itself, avoiding the hard-error part.Especially, the fault recovery ca... [more] RECONF2012-11
pp.61-66
CPSY, DC, IPSJ-SLDM, IPSJ-EMB [detail] 2012-03-03
13:30
Miyagi   A Case Study of Supervisor Processor for Dependable System
Makoto Fujino, Yoshihiro Ichinomiya, Hiroki Tanaka, Sayaka Yoshiura, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2011-92 DC2011-96
Multicore processor is widely used in various systems. Although it will be used in harsh environment
such as in-vehicle... [more]
CPSY2011-92 DC2011-96
pp.199-204
VLD, CPSY, RECONF, IPSJ-SLDM [detail] 2012-01-26
14:45
Kanagawa Hiyoshi Campus, Keio University Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster
Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.) VLD2011-116 CPSY2011-79 RECONF2011-75
Parallel processing by PC cluster and hardware acceleration by FPGA are useful technologies in a field of high performan... [more] VLD2011-116 CPSY2011-79 RECONF2011-75
pp.147-152
VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM
(Joint) [detail]
2011-11-28
16:05
Miyazaki NewWelCity Miyazaki Fast soft-error recovery method for duplicated softcore processor system
Yoshihiro Ichinomiya, Makoto Fujino, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2011-42
This paper presents a technique for ensuring the reliability of the softcore processor which implemented with SRAM-based... [more] RECONF2011-42
pp.7-12
RECONF 2011-09-27
09:50
Aichi Nagoya Univ. A Basic Implementation of LUT-based Dynamic and Partial Reconfiguration from Remote Site
Hiroyuki Kawai (Hamamatsu Photonics), Moritoshi Yasunaga (Tsukuba Univ.) RECONF2011-34
In this study we implement a mechanism that makes it possible to execute dynamic and partial reconfigurationfrom remote ... [more] RECONF2011-34
pp.69-74
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
10:20
Kanagawa Keio Univ (Hiyoshi Campus) Evaluation of switchable AES S-box circuit using dynamic and partial reconfiguration
Naoko Yamada (Keio Univ.), Keisuke Iwai, Takakazu Kurokawa (NDA), Hideharu Amano (Keio Univ.) VLD2010-102 CPSY2010-57 RECONF2010-71
Recently, the threat of side channel attack to the hardware encryption circuits is increasing. In order
to cope with it... [more]
VLD2010-102 CPSY2010-57 RECONF2010-71
pp.127-132
RECONF, VLD, CPSY, IPSJ-SLDM [detail] 2011-01-18
14:30
Kanagawa Keio Univ (Hiyoshi Campus) Implementation of Dynamic Reconfigurable Processor with Multi-Accelerator
Shuhei Igari, Junji Kitamichi, Yuichi Okuyama, Kenichi Kuroda (Aizu Univ.) VLD2010-108 CPSY2010-63 RECONF2010-77
Recently, System on a Chip (SoC) has problems increasing of the scale of circuit and design cost, because SoC contains m... [more] VLD2010-108 CPSY2010-63 RECONF2010-77
pp.163-168
RECONF 2010-09-16
11:00
Shizuoka Shizuoka University (Faculty of Eng., Hall 2) Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration
Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.) RECONF2010-18
In this paper, we develop an on-chip pattern recognition system.
The feature of this system is that two Microblaze core... [more]
RECONF2010-18
pp.1-6
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